Nonvolatile semiconductor memory device

ABSTRACT

A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2 m  (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is “m”. Specifically, when the number is determined such that 2 2 =4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to an electrically erasableprogrammable read-only memory (EEPROM) device, and more particularly toan EEPROM storing data of a multilevel.

[0002] The present application is based on Japanese Patent Application.No. 8-61352, Japanese Patent Application. No. 8-61443, Japanese PatentApplication. No. 8-61444 and Japanese Patent Application. No. 8-61449,the content of which is incorporated herein by reference.

[0003] As one of a means for increasing the capacity of an EEPROM, amultilevel storing EEPROM has been known capable of causing n(n≧3)-level information to be stored in one memory cell. A four-leveldata storing structure is arranged such that each cell is provided withone of four threshold voltages and the threshold voltages correspond to2-bit information expressed as “0 , 0”, “0, 1”, “1, 0” and “1, 1”. Toread data in the memory cell in which n-level information has beenstored, data read from the cell must be compared with (n−1) referencevoltages. Accordingly, (n−1) sense amplifiers have been required (referto, for example, Japanese Patent KOKAI Publication No. 61-117796). Afour-level data storing EEPROM must have three sense amplifiers.

[0004] Therefore, the four-level data storing EEPROM involves thestoring density in the memory cell being doubled as compared with theEEPROM having binary data storing cells. Although the area of the memorycells can be halved, the area of the sense amplifiers is tripled. Thus,a required high density structure cannot be formed. In particular, anEEPROM having a sense amplifier provided for each bit line for thepurpose of page reading cannot easily be formed into a large capacitystructure because the number of the sense amplifiers is enlargedexcessively.

[0005] A read-only memory has been disclosed in Japanese Patent KOKAIPublication No. 62-54896 which is capable of decreasing the number ofsense amplifiers by using an output from a sense amplifier, which hasdetermined cell data, to control the reference voltages of other senseamplifiers. However, the foregoing structure cannot be applied to awritable memory.

[0006] On the other hand, a multilevel data storing EEPROM for causing n(n≧3) types of threshold voltages to be stored in the memory cells mustdistribute the threshold voltages in each of narrow ranges when data tobe stored is written. Therefore, writing is performed little by littleand whether or not data has been written in each memory cell within arequired threshold voltage range is verified between writing operations.If a cell, in which data has not sufficiently been written, exists,additional writing of the cell has been performed. The foregoingtechnology is arranged to cause optimum writing to be performed for eachmemory cell and is known as “bit-by-bit verification”. The concept ofthe bit-by-bit verification has been disclosed in Japanese Patent KOKAIPublication No. 3-295098.

[0007] The technology disclosed in Japanese Patent KOKAI Publication No.3-295098 relates to a binary-data storing EEPROM. The bit-by-bitverification applicable to a multilevel data storing EEPROM has beendisclosed in Japanese Patent KOKAI Publication No. 7-93979. However, theapparatus disclosed in Japanese Patent KOKAI Publication No. 7-93979requires (n−1) sense amplifiers and (n−1) verify circuits. Although thememory cell is able to store larger quantity of data and thus a largequantity of data can be stored in a chip having the same area, the sizeof a circuit for controlling data read/write is enlarged excessively toform a highly integrated structure.

[0008] Moreover, the multilevel-data storing EEPROM involves the numberof bits of signals for use therein, in particular, the signals for usein the input/output data line being different from the number of bits ofsignals for use in a circuit substrate for establishing the connectionbetween the multilevel-data storing EEPROM with another integratedcircuit-apparatus, such as a processor. As a result, the multilevel-datastoring EEPROM must have a circuit for converting the number of bits ofthe signal for use in the outside portion of the apparatus into thenumber of bits of the signal for use in the apparatus.

[0009] When the number of multilevel data is n (n is a natural numbernot smaller than 3) in the conventional multilevel-data storing EEPROMhaving the verify means, (n−1) verify circuits must be provided.Therefore, also (n−1) sense amplifiers and (n−1) data latches must beprovided to correspond to the verify circuits. As a result, the size ofthe circuit connected to the bit line, that is, the size of thecolumn-system circuit, in particular, the number of the sense amplifiersand data latches cannot be reduced. Thus, a highly integrated structurecannot be realized.

[0010] Moreover, the circuit for converting the number of bits of thesignal for use in the outside portion of the apparatus and the number ofbits of the signal for use in the apparatus must be provided. Therefore,a highly integrated structure cannot be realized and a high speedinput/output operation cannot be performed.

BRIEF SUMMARY OF THE INVENTION

[0011] Accordingly, it is a first object of the present invention is toprovide a nonvolatile semiconductor memory device capable of decreasingthe size of a column-system circuit and realizing a highly integratedstructure.

[0012] A second object of the present invention is to provide anonvolatile semiconductor memory device capable of omitting a circuitfor converting the number of bits and realizing both highly integratedstructure and a high speed input/output operation.

[0013] The foregoing objects can be realized by the followingnonvolatile semiconductor memory device.

[0014] According to one aspect of the present invention, there isprovided a nonvolatile semiconductor memory device comprising:

[0015] a memory cell array in which memory cells for storing multileveldata are arranged in a matrix manner;

[0016] a bit line controller having latching means for latching data tobe written in the memory cell when data is written in the memory celland sensing/latching means for sensing and latching data read from thememory cell when data is read from the memory cell; and

[0017] a bit line for electrically connecting the bit line controllerand the memory cell to each other, supplying data from the latchingmeans to the memory cell when data is written in the memory cell andsupplying read data from the memory cell to the sensing/latching meanswhen data is read from the memory cell,

[0018] wherein when the number of multilevel data is n (n is a naturalnumber not smaller than 4), the number of the latching means and thenumber of the sensing/latching means are m (m satisfies 2^(m−1)<n ≦2^(m)(m is a natural number not smaller than 2).

[0019] According to the nonvolatile semiconductor memory device of thefirst aspect, when the number of multilevel data is n satisfyingn=2^(m), m is the same as the number of bits of data input/output lineswhich are electrically connected to the bit line controller, and one bitdata is assigned to each of the m latching means and the msensing/latching means.

[0020] According to the nonvolatile semiconductor memory device of thefirst aspect, when data is read from the memory cell, the msensing/latching means are sequentially operated from firstsensing/latching means assigned to a first bit which is the mostsignificant bit toward the m-th sensing/latching means assigned to them-th bit which is the least significant bit.

[0021] According to the nonvolatile semiconductor memory device of thefirst aspect, the first sensing/latching means assigned to the first bitwhich is the most significant bit compares read data supplied from thememory cell through the bit line with a first reference voltage tooutput a result of a comparison representing whether or not read data ishigher than the first reference voltage, and switches the level of asecond reference voltage to be provided for a second sensing/latchingmeans assigned to a second bit which is a next bit in accordance withthe output result of the comparison.

[0022] According to the nonvolatile semiconductor memory device of thefirst aspect, the level of the m-th reference voltage to be provided fora sensing/latching means assigned to the m-th bit which is the leastsignificant bit is switched 2^(m−1) times in accordance with a result ofa comparison between the (m−1)-th reference voltage provided for thesensing/latching means assigned to the (m−1)-th bit which is an upperbit and data read from the memory cell.

[0023] According to the nonvolatile semiconductor memory device of thefirst aspect, the number of bits of the data input/output line is thesame as the number of bits of write data to be supplied to the apparatusfrom outside of the apparatus and the number of bits of read data to beoutput from the inside portion of the apparatus to the outside of theapparatus.

[0024] According to the nonvolatile semiconductor memory device of thefirst aspect, write data is supplied to the latching means from outsideof the apparatus such that the number of bits of write data is notconverted, and read data is output from the sensing/latching means tothe outside of the apparatus such that the number of bits of read datais not converted.

[0025] According to the nonvolatile semiconductor memory device of thefirst aspect, 2^(m)=n-level data, which appears on one bit line, isconverted into m-bit and n-level data by the latching means and thesensing/latching means.

[0026] According to the nonvolatile semiconductor memory device of thefirst aspect, each of write data to be supplied from the latching meansto the memory cell through the bit line and read data to be suppliedfrom the memory cell to the sensing/latching means through the bit lineis n multilevel data, and the bit line distinguishes each of nmultilevel data in accordance with the level of voltage to supply datafrom the latching means to the memory cell and supply data from thememory cell to the sensing/latching means.

[0027] According to the nonvolatile semiconductor memory device of thefirst aspect, the memory cell for storing multilevel data includes atransistor having a variable threshold voltage, and the transistorhaving the variable threshold voltage distinguishes each of n multileveldata in accordance with the level of the threshold voltage and thenstore n multilevel data. According to a second aspect of the presentinvention, there is provided a nonvolatile semiconductor memory devicecomprising:

[0028] a memory cell array in which memory cells for storing multileveldata are arranged in a matrix manner;

[0029] a bit line controller having latching means for latching data tobe written in the memory cell when data is written in the memory cell,sensing/latching means for sensing and latching data read from thememory cell when data is read from the memory cell and verify means forperforming a verify operation to make a reference to data latched by thelatching means and arranged to be written in the memory cell; and

[0030] a bit line for electrically connecting the bit line controllerand the memory cell to each other, supplying data from the latchingmeans into the memory cell when data is written in the memory cell andsupplying read data from the memory cell to the sensing/latching meanswhen data is read from the memory cell,

[0031] wherein when the number of multilevel data is n (n is a naturalnumber not smaller than 4), the number of the latching means, the numberof the sensing/latching means and the number of the verify means are m(m satisfies 2^(m−1)<n ≦2^(m) (m is a natural number not smaller than2).

[0032] According to the nonvolatile semiconductor memory device of thesecond aspect, when the number of multilevel data is n satisfyingn=2^(m), m is the same as the number of bits of data input/output lineswhich are electrically connected to the bit line controller, and one bitdata is assigned to each of the m latching means and the msensing/latching means.

[0033] According to the nonvolatile semiconductor memory device of thesecond aspect, when data is read from the memory cell, the msensing/latching means are sequentially operated from firstsensing/latching means assigned to a first bit which is the mostsignificant bit toward the m-th sensing/latching means assigned to them-th bit which is the least significant bit, and when data is read fromthe memory cell for verification, the m sensing/latching means aresequentially operated from m-th sensing/latching means assigned to m-thbit which is the least significant bit toward the first sensing/latchingmeans assigned to the first bit which is the most significant bit.

[0034] According to the nonvolatile semiconductor memory device of thesecond aspect, when data is read from the memory cell, the firstsensing/latching means assigned to the first bit which is the mostsignificant bit compares read data supplied from the memory cell throughthe bit line with a first reference voltage to output a result of acomparison representing whether or not read data is higher than thefirst reference voltage, and switches the level of a second referencevoltage to be provided for a second sensing/latching means assigned to asecond bit which is a next bit in accordance with the output result ofthe comparison, and when data is read from the memory cell forverification, the level of the second reference voltage to be providedfor the second sensing/latching means assigned to the second bit whichis the next bit is switched in accordance with read data latched by thefirst latching means assigned to the first bit which is the mostsignificant bit.

[0035] According to the nonvolatile semiconductor memory device of thesecond aspect, when data is read from the memory cell, the level of them-th reference voltage to be provided for a sensing/latching meansassigned to the m-th bit which is the least significant bit is switched2^(m−1) times in accordance with a result of a comparison between the(m−1)-th reference voltage provided for the sensing/latching meansassigned to the (m−1)-th bit which is an upper bit and data read fromthe memory cell.

[0036] According to the nonvolatile semiconductor memory device of thesecond aspect, when data is read from the memory cell, thesensing/latching means converts 2^(m)=n-level data read to one bit lineinto n m-bit read data, when data is written in the memory cell, thelatching means supplies m-bit n-level write data to data writing circuitfor converting data into 2^(m)=n-level write data for one bit line, andm-bit and n-level read data and m-bit and n-level write data aresupplied as different data.

[0037] According to the nonvolatile semiconductor memory device of thesecond aspect, when data is read from the memory cell for verification,the latching means compares m-bit n-level write data with 2^(m)=n-leveldata read to one bit line, activates the verify means when the writedata and the read data coincide with each other and deactivates theverify means when the write data and the read data do not coincide witheach other.

[0038] According to the nonvolatile semiconductor memory device of thesecond aspect, the number of bits of the data input/output lines is thesame as each of the number of bits of write data to be supplied fromoutside of the apparatus into the apparatus and the number of bits ofread data to be output from the inside portion of the apparatus to theoutside of the apparatus.

[0039] According to the nonvolatile semiconductor memory device of thesecond aspect, write data is supplied from the outside of the apparatusto the latching means such that the number of bits of write data is notconverted, and read data is output from the sensing/latching means tothe outside of the apparatus such that the number of bits of read datais not converted.

[0040] According to the nonvolatile semiconductor memory device of thesecond aspect, each of write data to be supplied from the latching meansto the memory cell through the bit line and read data to be suppliedfrom the memory cell to the sensing/latching means through the bit lineis n multilevel data, and the bit line distinguishes each of nmultilevel data in accordance with the level of voltage to supply datafrom the latching means to the memory cell and supply data from thememory cell to the sensing/latching means.

[0041] According to the nonvolatile semiconductor memory device of thesecond aspect, each of write data to be supplied from the latching meansto the memory cell through the bit line and read data to be suppliedfrom the memory cell to the sensing/latching means through the bit lineis n multilevel data, and the bit line distinguishes each of nmultilevel data in accordance with the level of voltage to supply datafrom the latching means to the memory cell and supply data from thememory cell to the sensing/latching means.

[0042] According to the nonvolatile semiconductor memory device of thesecond aspect, the memory cell for storing multilevel data includes atransistor having a variable threshold voltage, and the transistorhaving the variable threshold voltage distinguishes each of n multileveldata in accordance with the level of the threshold voltage and thenstore n multilevel data.

[0043] According to a third aspect of the present invention, there isprovided a nonvolatile semiconductor memory device comprising:

[0044] a memory cell array in which memory cells for storing multileveldata are arranged in a matrix manner;

[0045] a bit line controller having latching function for latching datato be written in the memory cell when data is written in the memory celland sensing/latching function for sensing and latching data read fromthe memory cell when data is read from the memory cell and in which whenthe number of multilevel data is n (n is a natural number not smallerthan 4), the number of the latching function and the number of thesensing/latching function are m (m satisfies 2^(m−1)<n ≦2^(m) (m is anatural number not smaller than 2);

[0046] a bit line for electrically connecting the bit line controllerand the memory cell to each other, supplying data from the latchingfunction into the memory cell when data is written in the memory celland supplying read data from the memory cell to the sensing/latchingfunction when data is read from the memory cell;

[0047] a writing circuit for selecting write control voltagecorresponding to multilevel data in accordance with write data latchedby the latching function when data is written in the memory cell andapplying selected write control voltage to the bit line; and

[0048] a verify circuit for verifying data written in the memory cell,

[0049] wherein the verify circuit and the writing circuit is controlledin accordance with n write data latched by the latching function.

[0050] According to the nonvolatile semiconductor memory device of thethird aspect, the latch function updates write data latched in the latchfunction to non-changed memory cell data when data has been written inthe memory cell in a case where a result of verify read operation isvalid.

[0051] According to the nonvolatile semiconductor memory device of thethird aspect, data to be input to the latch function is controlled bythe verify circuit and the writing circuit in accordance with latchedwrite data in order to prevent change of updated write data during averify read operation.

[0052] According to a fourth aspect of the present invention, there isprovided a nonvolatile semiconductor memory device comprising a memorycell array formed of a plurality of memories each having a chargestorage portion capable of storing n-level (n>3) data, a plurality ofbit lines, a plurality of word lines, a plurality of program controllersand a plurality of data circuits, wherein the program controller selectsa memory cell and applies write voltage to the selected memory cell, thedata circuit is formed of m latches when m is a natural numbersatisfying 2^(m−1)<n≦2^(m), holds first, second, . . . , n-th logicallevel write control data for controlling write control voltages to beapplied to corresponding memory cells selected by the program controlcircuit, applies the write control voltages to the corresponding memorycells, selectively detects only a write state of the memory cellcorresponding to the data circuit storing the write control data of alogical level except the first logical level, changes the logical levelof the write control data in the data circuit corresponding to thememory cell which has brought to a predetermined write state to thefirst logical level, holds the logical level of write control data inthe data circuit corresponding to the memory cell which has not reachedthe predetermined write state, and holds the logical level of writecontrol data in the data circuit storing first logical level writecontrol data in the first logical level, and write data is updated inaccordance with the combination of states of m latches.

[0053] According to the nonvolatile semiconductor memory device of thefourth aspect, a verify circuit for updating write data generates writecontrol voltage.

[0054] According to a fifth aspect of the present invention, there isprovided a nonvolatile semiconductor memory device comprising:

[0055] a memory cell array in which memory cells for storing multileveldata are arranged in a matrix manner;

[0056] a bit line controller having data latch/sense amplifier forlatching data to be written in the memory cell when data is written inthe memory cell and sensing and latching data read from the memory cellwhen data is read from the memory cell such that when the number ofmultilevel data is 2^(m) (m is a natural number not smaller than2)=n-level, the number of the data latch/sense amplifier is m;

[0057] a bit line for connecting the data latch/sense amplifier and thememory cell to each other, supplying data from the data latch/senseamplifier into the memory cell when data is written in the memory celland supplying read data from the memory cell to the data latch/senseamplifier when data is read from the memory cell;,

[0058] a writing circuit for selecting write control voltagecorresponding to multilevel data in accordance with write data latchedby the data latch/sense amplifier when data is written in the memorycell and applying selected write control voltage to the bit line; and

[0059] a verify circuit for verifying whether or not written data hasbeen brought to a required date storing state after data has beenwritten in the memory cell.

[0060] According to a sixth aspect of the present invention, there isprovided a nonvolatile semiconductor memory device comprising:

[0061] a memory cell array in which memory cells for storing n-level (nis a natural number not smaller than 3) which can electrically berewritten are arranged in a matrix manner;

[0062] threshold detection means for electrically charging the bit lineconnected to the memory cell through the memory cell and outputtingmultilevel data in the memory cell as a multilevel level potential tothe bit line;

[0063] a sense amplifier for sensing the multilevel level bit linepotential charged by the threshold detection means;

[0064] first, second, . . . , m-th data circuits for storing data to bewritten in the memory cell;

[0065] verify means for verifying whether or not the state after datahas been written in the memory cell has been a required data storingstate by using the threshold detection means; and

[0066] means for simultaneously updating contents of the data circuitformed of a data updating circuit for simultaneously updating thecontents of the data circuit to again write data in only a memory cellin which data has not been sufficiently written in accordance with thecontents of the data circuit and the state after data has been writtenin the memory cell,

[0067] wherein the data updating circuit makes a reference to thecontents of one data circuit.

[0068] According to a seventh aspect of the present invention, there isprovided a nonvolatile semiconductor memory device comprising:

[0069] a memory cell array in which memory cells for storing n-level (nis a natural number not smaller than 3) which can electrically berewritten are arranged in a matrix manner;

[0070] threshold detection means for electrically charging the bit lineconnected to the memory cell through the memory cell and outputtingmultilevel data in the memory cell as a multilevel level potential tothe bit line;

[0071] a sense amplifier for sensing the multilevel-level potential ofthe bit line electrically charged by the threshold detection means bymaking a comparison with a reference voltage;

[0072] first, second, . . . , m-th data circuits for storing data to bewritten in the memory cell;

[0073] verify means for verifying whether or not the state after datahas been written in the memory cell has been a required data storingstate by using the threshold detection means; and

[0074] means for simultaneously updating contents of the data circuit,which is formed of a data updating circuit for simultaneously updatingthe contents of the data circuit to again write data in only a memorycell in which data has not been sufficiently written in accordance withthe contents of the data circuit and the state after data has beenwritten in the memory cell,

[0075] wherein the data updating circuit makes a reference to thecontents of one data circuit, the means for simultaneously updatingcontents of the data circuit modifies the bit line to which the stateafter the memory cell writing operation has been performed is output andthe reference voltage in accordance with the contents of the datacircuit in order to cause the potential of the bit line to be sensed andstored as re-write data, holds the data storing state of the datacircuit until the potential of the bit line is modified, operates thedata circuit as a sense amplifier while storing the modified potentialof the bit line and simultaneously updates the contents of the datacircuit, and a writing operation and the simultaneous update of thecontents of the data circuit in accordance with the contents of the datacircuit are repeated until the memory cell is brought to a predeterminedwrite state so that data is electrically written.

[0076] According to the nonvolatile semiconductor memory device of thefifth, sixth and seventh aspects, the memory cell is a NAND cell havinga plurality of memory cell transistors, in series, connected, an end ofthe NAND cell is connected to the bit line through a first selectiongate, and another end of the NAND cell is connected to a source linethrough a second selection gate, the threshold detection means causesthe voltage of the source line to be transferred to the bit line throughthe NAND cell, and voltages of non-selected control gates and voltagesof the first and second selection gates are controlled in such a mannerthat voltage transfer performance of the non-selected memory cells andthe first and second selection transistors is improved such that thevoltage of the bit line is determined in accordance with the thresholdvoltage of the selected memory cell.

[0077] According to an eighth aspect of the present invention, there isprovided a nonvolatile semiconductor memory device comprising:

[0078] a memory cell array in which memory cells for storing n-level (nis a natural number not smaller than 4) which can electrically berewritten are arranged in a matrix manner;

[0079] first, second, . . . , m-th (m is a natural number satisfying2^(m−1)<n≦2^(m)) data circuits for storing data to be written in thememory cell; and

[0080] verify means for verifying whether or not the state after datahas been written in the memory cell has been a required data storingstate.

[0081] According to a ninth aspect of the present invention, there isprovided a nonvolatile semiconductor memory device comprising:

[0082] a memory cell array in which memory cells for storing n-level (nis a natural number not smaller than 3) which can electrically berewritten are arranged in a matrix manner;

[0083] first, second, . . . , m-th (m is a natural number satisfying2^(m−1)<n<2^(m)) data circuits for storing data to be written in thememory cell;

[0084] verify means for verifying whether or not the state after datahas been written in the memory cell has been a required data storingstate; and

[0085] means for simultaneously updating contents of the data circuit,which is formed of a data updating circuit for simultaneously updatingthe contents of the data circuit to again write data in only a memorycell-in which data has not been sufficiently written in accordance withthe contents of the data circuit and the state after data has beenwritten in the memory cell,

[0086] wherein the data update circuit makes a reference to the contentsof one data circuit.

[0087] According to a tenth aspect of the present invention, there isprovided a nonvolatile semiconductor memory device comprising:

[0088] a memory cell array in which memory cells for storing n-level (nis a natural number not smaller than 4) which can electrically berewritten are arranged in a matrix manner;

[0089] threshold detection means for detecting the threshold voltage ofthe memory cell;

[0090] first, second, . . . , m-th (m is a natural number satisfying2^(m−1)<n≦2^(m)) data circuits for storing data to be written in thememory cell; and

[0091] verify means for verifying whether or not the state after datahas been written in the memory cell has been a required data storingstate,

[0092] wherein detection of the threshold voltage is performed such thatfirst threshold detection voltage is applied to a gate electrode of thememory cell to determine whether the memory cell is (i) in a “1” stateor (ii) in a “2 or more” state (i.e., “2”, “3”, . . . , or “n” state),second threshold detection voltage is applied to the gate electrode ofthe memory cell to determine whether the memory cell is (i) in the “1 or2” state (i.e., “1” or “2” state) or (ii) in a “3 or more” state (i.e.,“3”, “4”, . . . , or “n” state), and third to (n−1)-th thresholddetection voltage is applied to the gate electrode of the memory cell.

[0093] According to an eleventh aspect of the present invention, thereis provided a nonvolatile semiconductor memory device comprising:

[0094] a memory cell array in which memory cells for storing n-level (nis a natural number not smaller than 3) which can electrically berewritten are arranged in a matrix manner;

[0095] a data circuit for storing data to be written in the memory cell;and

[0096] verify means for verifying whether or not the state after datahas been written in the memory cell has been a required data storingstate,

[0097] wherein a writing operation is performed to realize n types ofwrite states such that first writing of memory cells, in which writingof k types (k is a natural number satisfying 2≦k<n) is performed, issubstantially simultaneously performed, and writing of a memory cell inwhich (n−k) types of writing states are performed is performed before orafter the first writing operation.

[0098] According to a twelfth aspect of the present invention, there isprovided a nonvolatile semiconductor memory device comprising:

[0099] a memory cell array in which memory cells for storing n-level (nis a natural number not smaller than 3) in which “1” state is an erasestate, and “2”, “3”, . . . , of “n” state is a write state and which canelectrically be rewritten are arranged in a matrix manner;

[0100] a data circuit for storing data to be written in the memory cell;and

[0101] verify means for verifying whether or not the state after datahas been written in the memory cell has been a required data storingstate,

[0102] wherein first writing of memory cells which are written in the“3”, . . . , or “n” state among the n types of writing operations issubstantially simultaneously performed, and writing to “2” state isperformed before or after the first writing operation.

[0103] According to the nonvolatile semiconductor memory device of thetwelfth aspect, threshold voltages for writing “1”, “2”, “3”, . . . , or“n” state satisfying the following relation;

[0104] “1” state<“2” state<“3” state<. . . <“n” state.

[0105] According to a thirteenth aspect of the present invention, thereis provided a nonvolatile semiconductor memory device comprising:

[0106] a memory cell array in which memory cells for storing n-level andhaving storing states of “1”, “2”, “3”, . . . , or “n” state (n is anatural number not smaller than 3) and being able to be electricallyrewritten are arranged in a matrix manner;

[0107] a signal line for communicating data with the memory cell; and

[0108] a read data storing circuit for storing data read from the memorycell,

[0109] wherein an i-th reading operation is performed such that thethreshold voltage of the memory cell is similar to “i” state, higherthan the “i” state or lower than the “i” state is determined, and readdata is stored in the data storing circuit, and

[0110] when a j-th reading operation is performed in which the thresholdvoltage of the memory cell is similar to “j” state, higher than the “j”state or lower than the “j” state is determined, the potential of thesignal line from which data in the memory cell has been output ischanged by making a reference to data stored in the data storingcircuit, and then the potential of the signal line is sensed.

[0111] According to a fourteenth aspect of the present invention, thereis provided a nonvolatile semiconductor memory device comprising:

[0112] a memory cell array in which memory cells for storing n-level (nis a natural number not smaller than 3) which can electrically berewritten are arranged in a matrix manner;

[0113] a signal line for communicating data with the memory cell;

[0114] a data circuit for storing data to be written in the memory cell;and

[0115] verify means for verifying whether or not the state after datahas been written in the memory cell has been a required data storingstate,

[0116] wherein reference to the potential of a signal line from whichdata to be written in the memory cell has been output is made two ormore times to update the contents of the data circuit in such a mannerthat the writing of a memory cell in which data has not beensufficiently written is again performed in accordance with the contentsof the data circuit and a state after data has been written in thememory cell.

[0117] According to a fifteenth aspect of the present invention, thereis provided a nonvolatile semiconductor memory device comprising:

[0118] a memory cell array in which memory cells for storing n-level (nis a natural number not smaller than 3) which can electrically berewritten are arranged in a matrix manner;

[0119] threshold detection means for detecting the threshold voltage ofthe memory cell;

[0120] a data circuit for storing data to be written in the memory cell;and

[0121] verify means for verifying whether or not the state after datahas been written in the memory cell has been a required data storingstate,

[0122] wherein detection of the threshold voltage is performed such thatfirst threshold detection voltage is applied to a gate electrode of thememory cell to determine whether the memory cell is (i) in a “1” stateor (ii) in a “2 or more” state (i.e., “2”, “3”, or “n” state), secondthreshold detection voltage is applied to the gate electrode of thememory cell to determine whether the memory cell is (i) in “1 or 2”state (i.e., “1” or “2” state) or (ii) “3 or more” state (i.e., “3”,“4”, . . . , or “n” state”), third to (n−1)-th threshold detectionvoltage is applied to the gate electrode of the memory cell, andreference to the potential of a signal line from which data to bewritten in the memory cell has been output is made two or more times toupdate the contents of the data circuit in such a manner that thewriting of a memory cell in which data has not been sufficiently writtenis again performed in accordance with the contents of the data circuitand a state of the memory cell after data has been written.

[0123] According to a sixteenth aspect of the present invention, thereis provided a nonvolatile semiconductor memory device comprising:

[0124] a memory cell array in which memory cells for storing n-level (nis a natural number not smaller than 3) and being able to beelectrically rewritten are arranged in a matrix manner;

[0125] m data circuits for storing data to be written in the memorycell;

[0126] verify means for verifying whether or not the state of the memorycell after data has been written has been a required data storing state;and

[0127] means for simultaneously updating contents of the data circuit,which is formed of a data updating circuit for simultaneously updatingthe contents of the data circuit to again write data in only a memorycell in which data has not been sufficiently written in accordance withthe contents of the data circuit and the state of the memory cell afterdata has been written,

[0128] wherein the data update circuit makes a reference to the contentsof one data circuit.

[0129] According to a seventeenth aspect of the present invention, thereis provided a nonvolatile semiconductor memory device comprising:

[0130] means for charging the bit line with one of bit line writepotentials corresponding to multilevel data when multilevel data iswritten in the memory cell and brining the bit line to an electricallyfloating state; and

[0131] means for causing the potential of the bit line to have a bitline write control potential determined in accordance with multileveldata by increasing, decreasing or maintaining the quantity of charge ofthe bit line.

[0132] According to an eighteenth aspect of the present invention, thereis provided a nonvolatile semiconductor memory device comprising:

[0133] a memory cell array in which memory cells for storing binary orhigher level data are arranged in a matrix manner;

[0134] a bit line used for writing data in the memory cell and readingdata from the memory cell; and

[0135] a bit line controller for making the bit line to a predeterminedpotential and then bringing the bit line to an electrically floatingstate,

[0136] wherein the bit line is set to a predetermined potential and thenis brought to an electrically floating state, and when data is writtenin the memory cell, the predetermined potential of the bit line is usedas one of bit line write control voltages.

[0137] According to a nineteenth aspect of the present invention, thereis provided a nonvolatile semiconductor memory device comprising:

[0138] a memory cell array in which memory cells for storing binary orhigher level data are arranged in a matrix manner;

[0139] a bit line for transferring data to be written in the memory celland data read from the memory cell;

[0140] a first circuit connected to the bit line to make the potentialof the bit line to a predetermined level before data is written in thememory cell and bring the bit line to an electrically floating state;and

[0141] a second circuit connected to the bit line for maintaining thepotential of the bit line at the predetermined level when one of binaryor higher level data is written in a selected memory cell and shiftingthe potential of the bit line to a level different from thepredetermined level when another binary or higher level data is writtenin a selected memory cell.

[0142] According to the nonvolatile semiconductor memory device of thenineteenth aspect, the second circuit includes a flip-flop circuit, andthe flip-flop circuit stores data to be written when data is written inthe memory cell.

[0143] According to the nonvolatile semiconductor memory device of thenineteenth aspect, the flip-flop circuit maintains the potential of thebit line at the predetermined level or shifts the potential to a leveldifferent from the predetermined level in accordance with stored data tobe written when data is written in the memory cell.

[0144] According to the nonvolatile semiconductor memory device of thenineteenth aspect, the flip-flop circuit amplifies and stores read datawhen data is read from the memory cell.

[0145] According to the nonvolatile semiconductor memory device of thenineteenth aspect, the number of data to be stored by the memory cell isn (n≧2), the number of the flip-flop circuits for storing data to bewritten in the memory cell and amplifies and stores data read from thememory cell is (n−1).

[0146] According to the nonvolatile semiconductor memory device of thenineteenth aspect, write data stored by (n−1) flip-flop circuits ischanged to another data after a verify operation has been completed.

[0147] According to the nonvolatile semiconductor memory device of thenineteenth aspect, there is further provided a write completiondetecting circuit for detecting change of write data stored by (n−1)flip-flop circuits into another data to complete a writing operationwhen the write completion detecting circuit has detected the change.

[0148] According to a twentieth aspect of the present invention, thereis provided a nonvolatile semiconductor memory device comprising:

[0149] a memory cell array in which memory cell for storing binary orhigher level data are arranged in a matrix manner;

[0150] a bit line connected to a source and a drain of the memory cell;and

[0151] a bit line controller connected between the bit line and a datainput/output line,

[0152] wherein the bit line controller has a charging circuit forcharging the bit line before a writing operation, a write data storingportion for storing write data supplied to the data input/output line,and a data controller for maintaining the potential of the bit line atthe charged level or shifting the potential from the charged level inaccordance with write data stored by the write-data storing portion.

[0153] According to the nonvolatile semiconductor memory device of thetwenties aspect, the data controller includes a flip-flop circuit, andthe flip-flop circuit stores write data supplied to the datainput/output line when data is written in the memory cell.

[0154] According to the nonvolatile semiconductor memory device of thetwenties aspect, the flip-flop circuit amplifies data read to the bitline to supply read data to the data input/output line.

[0155] According to the nonvolatile semiconductor memory device of thetwenties aspect, when the number of data to be stored by the memory cellis n (n−2), the number of the flip-flop circuits for storing data to bewritten in the memory cell and amplifies and stores data read from thememory cell is (n−1).

[0156] According to the nonvolatile semiconductor memory device of thetwenties aspect, write data to be stored by (n−1) flip-flop circuits ischanged to another data after a verification operation has beencompleted.

[0157] According to the nonvolatile semiconductor memory device of thetwenties aspect, there is further provided a write completion detectingcircuit for detecting change of write data stored by (n−1) flip-flopcircuits into another data to complete a writing operation when thewrite completion detecting circuit has detected the change.

[0158] According to the nonvolatile semiconductor memory device of thetwenties aspect, the charging circuit charges the bit line to a powersupply potential.

[0159] According to the nonvolatile semiconductor memory device of thetwenties aspect, the data controller maintains the potential of the bitline at the power supply potential or makes the potential to be lowerthan the power supply potential.

[0160] According to the nonvolatile semiconductor memory device of thetwenties aspect, the charging circuit charges the bit line to apotential between a ground voltage and the power supply voltage.

[0161] According to the nonvolatile semiconductor memory device of thetwenties aspect, the data controller maintains the potential of the bitline at the intermediate potential, makes the potential to be lower thanthe intermediate potential or makes the potential to be higher than theintermediate potential in accordance with write data stored by the writedata storing portion included in the data controller.

[0162] Additional objects and advantages of the present invention willbe set forth in the description which follows, and in part will beobvious from the description, or may be learned by practice of thepresent invention.

[0163] The objects and advantages of the present invention may berealized and obtained by means of the instrumentalities and combinationsparticularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0164] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the present invention and, together with the generaldescription given above and the detailed description of the preferredembodiments given below, serve to explain the principles of the presentinvention in which:

[0165]FIG. 1 is a diagram showing the structure of a multilevel datastoring EEPROM according to a first embodiment of the present invention;

[0166]FIG. 2 is a diagram showing the structure of a memory cell arrayand a column-system circuit shown in FIG. 1;

[0167]FIG. 3A is a circuit diagram showing the NAND cell shown in FIG.2;

[0168]FIG. 3B is a cross sectional view showing the structure of thememory cell transistor;

[0169]FIG. 4A shows a voltage input state when data is read from theNAND cell;

[0170]FIG. 4B is a graph showing waveforms of input voltages andwaveforms of outputs appearing on the bit line;

[0171]FIG. 5 is a graph showing a state of voltages on the bit line;

[0172]FIG. 6 shows a state of voltage input when data is written in theNAND cell;

[0173]FIG. 7 is a diagram showing the structure of a data circuit in abit line controller of a NAND type EEPROM according to the firstembodiment of the present invention;

[0174]FIG. 8 is a circuit diagram showing the writing circuit shown inFIG. 7;

[0175]FIG. 9 is a diagram showing the structure of a NAND type EEPROMaccording to a second embodiment of the present invention;

[0176]FIG. 10 is a circuit diagram showing the bit line controller shownin FIG. 9;

[0177]FIG. 11 is a circuit diagram showing an example of the flip-flopcircuit shown in FIG. 10;

[0178]FIG. 12 is a circuit diagram showing another example of theflip-flop circuit shown in FIG. 10;

[0179]FIG. 13 is an operation waveform showing a data reading operation;

[0180]FIG. 14 is an operation waveform showing a data writing operation;

[0181]FIG. 15 is a table showing states of nodes VL1-1, VL2-1, VL1-2 andVL2-2 after four-level data has been read;

[0182]FIG. 16 is a table showing states of nodes VL1-1, VL2-1, VL1-2 andVL2-2 when four-level data is written;

[0183]FIG. 17 is a table showing states of nodes VL1-1, VL2-1, VL1-2 andVL2-2 during verification of four-level data;

[0184]FIG. 18 is a diagram showing the structures of a memory cell arrayand a column-system circuit of an EEPROM according to a third embodimentof the present invention;

[0185]FIG. 19 is a diagram showing the structure of a multilevel datastoring NAND type EEPROM according to a fourth embodiment of the presentinvention;

[0186]FIG. 20 is a diagram showing the-structures of the memory cellarray and the column-system circuit shown in FIG. 19;

[0187]FIG. 21 is a graph showing distribution of threshold voltages of amemory cell transistor when multilevel data is stored;

[0188]FIG. 22 is a circuit diagram showing the bit line controller shownin FIG. 20;

[0189]FIG. 23 is an operation waveform showing a usual reading operationand a verify operation;

[0190]FIG. 24 is an operation waveform showing the usual readingoperation and the verify operation;

[0191]FIG. 25 is an operation waveform showing the usual readingoperation and the verify operation;

[0192]FIG. 26 is an operation waveform showing a writing operation;

[0193]FIG. 27 is an operation waveform showing the writing operation;

[0194]FIG. 28 is an operation waveform showing the writing operation;

[0195]FIG. 29 is a table showing the relationship between the thresholdvoltages and latched data of the memory cell transistor;

[0196]FIG. 30 is a table showing the relationship between the latcheddata and the threshold voltages of the memory cell transistor;

[0197]FIG. 31 is a diagram showing the structure of a multilevel datastoring NAND type EEPROM according to a fifth embodiment of the presentinvention;

[0198]FIG. 32 is a diagram showing the structures of the memory cellarray and the column-system circuit shown in FIG. 31;

[0199]FIG. 33 is a circuit diagram showing the bit line controller shownin FIG. 31;

[0200]FIG. 34 is an operation waveform showing the usual readingoperation and the verify operation;

[0201]FIG. 35 is an operation waveform showing a writing operation;

[0202]FIG. 36 is a diagram showing the structure of a multilevel datastoring NAND type EEPROM according to a sixth embodiment of the presentinvention;

[0203]FIG. 37 is a diagram showing the structures of the cell array andthe column-system circuit shown in FIG. 36;

[0204]FIG. 38A shows voltage input states when data is read from thememory cell shown in FIG. 37;

[0205]FIG. 38B shows waveforms of input voltages and output waveformappearing on the bit line;

[0206]FIG. 39 is a graph showing output voltage appearing on the bitline and the number of the memory cells;

[0207]FIG. 40 is a circuit diagram showing the bit line controller shownin FIG. 37;

[0208]FIG. 41 is an operation waveform showing the reading operation;

[0209]FIG. 42 is a table showing data sensed and latched by a flip-flop;

[0210]FIG. 43 is a table showing write data latched by the flip-flop;

[0211]FIG. 44 is an operation waveform showing the writing operation;

[0212]FIG. 45 is an operation waveform showing the verify readingoperation;

[0213]FIG. 46 is a graph showing distribution of threshold voltages ofthe memory cell transistor when four-level data is stored by theapparatus according to the seventh embodiment of the present invention;

[0214]FIG. 47 is a circuit diagram showing the bit line controller ofthe EEPROM according to the seventh embodiment;

[0215]FIG. 48 is an operation waveform showing the reading operation;

[0216]FIG. 49 is a table showing read data sensed and latched by theflip-flop;

[0217]FIG. 50 is a table showing read data sensed and latched by theflip-flop;

[0218]FIG. 51 is a schematic view showing the writing operation;

[0219]FIG. 52 is a table showing write data latched by the flip-flop;

[0220]FIG. 53 is an operation waveform showing the writing operation(program first cycle);

[0221]FIG. 54 is an operation waveform showing the verify readingoperation (verify read first cycle);

[0222]FIG. 55 is a table showing data latched by the flip-flop circuit;

[0223]FIG. 56 is a circuit diagram showing a data circuit having atransistor for simultaneously detecting completion of writing;

[0224]FIG. 57 is an operation waveform showing the writing operation(program first cycle);

[0225]FIG. 58 is an operation waveform showing the verify readingoperation (verify read second cycle);

[0226]FIG. 59 is a table showing data latched by the flip-flop;

[0227]FIG. 60 is a operation waveform showing another verify readingoperation (verify read first cycle);

[0228]FIG. 61 is another circuit diagram showing the data circuit;

[0229]FIG. 62 is another circuit diagram showing the data circuit;

[0230]FIG. 63 is a circuit diagram showing a bit line controller of theEEPROM according to an eighth embodiment of the present invention;

[0231]FIG. 64 is an operation waveform showing the reading operation;

[0232]FIG. 65 is a table showing read data sensed and latched by theflip-flop;

[0233]FIG. 66 is a table showing read data sensed and latched by theflip-flop;

[0234]FIG. 67 is a table showing write data latched by the flip-flop;

[0235]FIG. 68 is an operation waveform showing the writing operation;

[0236]FIG. 69 is an operation waveform showing the verify readoperation;

[0237]FIG. 70 is an operation waveform showing the verify readoperation;

[0238]FIG. 71 is an operation waveform showing another verify readoperation;

[0239]FIG. 72 is another circuit diagram showing the data circuit;

[0240]FIG. 73 is another circuit diagram showing the data circuit;

[0241]FIG. 74 is another circuit diagram showing the data circuit;

[0242]FIG. 75 is another circuit diagram showing the data circuit;

[0243]FIG. 76 is a circuit diagram showing the bit line controller of anEEPROM according to a ninth embodiment of the present invention;

[0244]FIG. 77 is an operation waveform showing the reading operation;

[0245]FIG. 78 is a table showing read data sensed and latched by theflip-flop;

[0246]FIG. 79 is a table showing read data sensed and latched by theflip-flop;

[0247]FIG. 80 is a diagram showing the structure of the EEPROM having amodified column structure;

[0248]FIG. 81 is a diagram showing the structure of a multilevel datastoring EEPROM according to a tenth embodiment of the present invention;

[0249]FIG. 82 is a diagram showing the structures of the memory cellarray and the column-system circuit shown-in FIG. 81;

[0250]FIG. 83 is a graph showing the relationship between the thresholdvoltages and four writing states of the memory cell transistor when theEEPROM is a four-level data storing memory;

[0251]FIG. 84 is a diagram showing the structure of the bit linecontroller shown in FIG. 82;

[0252]FIG. 85 is a table showing the relationship between write data andpotential level of the data input/output line;

[0253]FIG. 86 is a table showing the relationship between read data andpotential level of the data input/-output line;

[0254]FIG. 87 is a operation waveform showing the writing operation ofthe EEPROM having the data circuit shown in FIG. 84;

[0255]FIG. 88A is a diagram showing the structure of a data controllerof a nonvolatile semiconductor memory device according to a tenthembodiment of the present invention;

[0256]FIG. 88B is a circuit diagram showing the flip-flop circuit shownin FIG. 88A;

[0257]FIG. 89 is an operation waveform showing the reading operation ofthe EEPROM having the data controller shown in FIGS. 88A and 88B and theverify reading operation which is performed after the writing operation;

[0258]FIG. 90A is a diagram showing another structure of the datacontroller of the semiconductor memory device according to the firstembodiment of the present invention;

[0259]FIG. 90B is a circuit diagram showing the flip-flop circuit shownin FIG. 90A;

[0260]FIG. 91 is an operation waveform showing the reading operation ofthe EEPROM having-the data controller shown in FIGS. 90A and 90B and theverify operation which is performed after the writing operation;

[0261]FIG. 92 is a table showing state of change of write data in thedata circuit;

[0262]FIG. 93 is a circuit diagram showing a circuit for detectingcompletion of writing of data;

[0263]FIG. 94 is a diagram showing the structure of a data circuit ofthe multilevel data storing EEPROM according to an eleventh embodimentof the present invention;

[0264]FIG. 95 is an operation waveform showing the writing operation ofthe EEPROM having the data circuit shown in FIG. 94;

[0265]FIG. 96 is a diagram showing the structure of the multilevel datastoring EEPROM according to a twelfth embodiment of the presentinvention;

[0266]FIG. 97 is a diagram showing the structures of the memory cellarray and the column-system circuit shown in FIG. 96;

[0267]FIG. 98 is a table showing the threshold voltages and threewriting states of the memory cell transistor when the EEPROM is able tomemory ternary data;

[0268]FIG. 99 is a diagram showing the structure of the data circuitshown in FIG. 97;

[0269]FIG. 100 is a diagram showing a data controller of thesemiconductor memory device according to the twelfth embodiment of thepresent invention;

[0270]FIG. 101 is a circuit diagram showing a first flip-flop circuitshown in FIG. 100;

[0271]FIG. 102 is a circuit diagram showing a second flip-flop circuitshown in FIG. 100;

[0272]FIG. 103 is a table showing the relationship between write dataand potential levels of the data input/output line;

[0273]FIG. 104 is a table showing the relationship between read data andthe potential levels of the data input/output line;

[0274]FIG. 105 is an operation waveform showing the writing operation ofthe EEPROM according to the twelfth embodiment of the present invention;

[0275]FIG. 106 is an operation waveform showing the reading operation ofthe EEPROM according to the twelfth embodiment of the present invention;

[0276]FIG. 107 is an operation waveform showing the verify readingoperation of the EEPROM according to the twelfth embodiment of thepresent invention;

[0277]FIG. 108 is an operation waveform showing the verify readingoperation of the EEPROM according to the twelfth embodiment of thepresent invention;

[0278]FIG. 109 is a table showing a state of change of write data in thedata circuit;

[0279]FIG. 110 is a diagram showing the structures of the memory cellarray and the column-system circuit of the EEPROM according to athirteenth embodiment of the present invention;

[0280]FIG. 111 is a diagram showing the structures of the memory cellarray and the column-system circuit of the EEPROM according to thefourteenth embodiment of the present invention;

[0281]FIG. 112 is a diagram showing a memory cell array having NOR cellsintegrated therein;

[0282]FIG. 113 is a diagram showing a memory cell array having other NORcells integrated therein;

[0283]FIG. 114 is a diagram showing a memory cell array having groundarray cells integrated therein;

[0284]FIG. 115 is a diagram showing a memory cell array having groundarray cells integrated therein;

[0285]FIG. 116 is a diagram showing a memory cell array having alternateground array cells integrated therein;

[0286]FIG. 117 is a diagram showing a memory cell array having otheralternate ground array cells integrated therein;

[0287]FIG. 118 is a diagram showing a memory cell array having DINORcells integrated therein; and

[0288]FIG. 119 is a diagram showing a memory cell array having AND cellsintegrated therein.

DETAILED DESCRIPTION OF THE INVENTION

[0289] A preferred embodiment of a nonvolatile semiconductor memorydevice according to the present invention will now be described withreference to the accompanying drawings.

[0290] (First Embodiment)

[0291]FIG. 1 is a diagram showing the structure of a multilevel storingEEPROM according to a first embodiment of the present invention. Arow-system circuit 2 and a column-system circuit 3 are connected to amemory cell array 1 having memory cells (not shown) arranged in a matrixmanner.

[0292] The row-system circuit 2 includes a row decoder 2A for receivingan address signal output from an address input/output circuit(hereinafter called as an “address buffer”) 4 to select a row of thememory cell array in response to the supplied address signal, and a wordline driver 2B for driving a word line of the memory cell array inaccordance with an output from the row decoder 2A. In this embodiment, aNAND type EEPROM will now be described which comprises word lines whichare selection gates (SG) and control gates (CG). Therefore, the wordline driver 2B is sometimes called a control gate/selection gate driver.The control gate/selection gate driver 2B selects a selection gate (SG)and a control gate (CG) in response to the address signal to applywriting voltage, reading voltage and the like to the selected selectiongate and control gate.

[0293] The column-system circuit 3 includes a column decoder 3A forreceiving the address signal output from the address buffer 4 to selecta column of the memory cell array and a column selection line driver 3Bfor driving the column selection line for selecting a column of thememory cell array in accordance with an output from the column decoder3A.

[0294] Moreover, the column-system circuit 3 includes a bit linecontroller (including data circuits to be described later) 3C fortemporarily storing data to be written in the memory cell and readingdata in the memory cell. The bit line controller 3C is connected to adata input/output circuit (data input/output buffer) 5. The bit linecontroller 3C receives write data from the data input/output buffer 5when data is written to output the received write data to the memorycell array 1.

[0295] On the other hand, the bit line controller 3C receives data readfrom the memory cell to output received data to the data input/outputbuffer 5. The data input/output buffer 5 controls input/output of datasuch that it introduces write data supplied from outside of the EEPROMand outputs data read from the memory core portion 1A to the outside ofthe EEPROM. A write completion detecting circuit 18 detects whether ornot writing of data has been completed in accordance with an output fromthe bit line controller 3C.

[0296]FIG. 2 is a diagram showing the structure of the memory cell array1 and the column-system circuit 3 (in particular, the bit linecontroller 3C) shown in FIG. 1.

[0297] As shown in FIG. 2, the memory cell array 1 has memory cells MCarranged in the matrix manner. The EEPROM according to this embodimenthas a structure such that one cell MC includes a plurality of memorycell transistors M1 to M4 connected in series so that a NAND cell MC isformed. An end of the cell MC is connected to bit line BL0 to BLmthrough a selection transistor S1, while another end of the same isconnected to a source line VS through a selection transistor S2. A groupof the memory cell transistors M sharing the control gate CG forms aunit called a “page”. Data is written and read simultaneously in pageunits. A group of memory cell transistors M connected to four controlgates CG1 to CG4 forms a unit called a “block”. The page and blockrespectively are selected by control gate/selection gate driver (notshown).

[0298] Data circuits 6-0 to 6-m respectively are connected between thebit lines BL0 to BLm and data input/output line I/O. The data circuits6-0 to 6-m have means for temporarily storing data to be written in thememory cell and means for sensing and temporarily storing data read fromthe memory cell.

[0299] The structure of the NAND cell shown in FIG. 2 will now bedescribed. FIG. 3A is a circuit diagram, and FIG. 3B is a crosssectional view showing the structure of the memory cell transistor. Thememory cell array 1 shown in FIG. 2 is formed on a p-type well or ap-type substrate. As shown in FIG. 3A, the NAND cells integrated in thememory cell array 1 are structured such that, for example, four memorycell transistors M1 to M4 are connected in series. An end of the cell MCis, through the selection transistor S1, connected to bit line BL, whileanother end of the same is connected to common source line VS throughselection transistor S2. The gates of the transistors M1 to M4respectively are connected to control gates CG1 to CG4.

[0300] As shown in FIG. 3B, one memory cell transistor M has a floatinggate (a charge storage layer) and the control gate CG and stores data inaccordance with the quantity of electrons stored in the floating gate.The quantity of the stored electrons can be read as the thresholdvoltage of the memory cell transistor.

[0301] The operation of the NAND cell MC shown in FIGS. 3A and 3B willnow be described such that a case in which the memory cell transistor M2is selected is taken as an example.

[0302] The operation for reading data from the NAND cell MC will now bedescribed. FIG. 4A shows a state where voltage is applied, and FIG. 4Bis a graph showing waveforms of gate voltages of the transistors andwaveforms of outputs appearing the bit lines.

[0303] Initially, the bit line BL is previously reset to 0V. After theresetting operation, the bit line BL is brought to a floating state.Then, voltages as shown in FIGS. 4A and 4B are applied to the NAND cellto read data. The bit line BL is electrically charged from the commonsource line VS through the selection transistors S1 and S2 and thememory cell transistors M1 to M4. The voltages of the selection gate andthe control gate are controlled in such a manner that the potential ofthe charged bit line BL is determined in accordance with the thresholdvoltage of the memory cell transistor M.

[0304] In this example, while employing the waveforms shown in FIG. 4B,the selection gates SG1 and SG2 and the control gates CG1, CG3 and CG4are set to be 6V, the selected control gate CG2 is set to be 3V and thecommon source line VS is set to be 3V. As a result, voltage obtained bysubtracting the threshold voltage of the memory cell transistor M2 fromthe voltage of the control gate CG2 appears at the selected control gateBL.

[0305] An example of the threshold voltage of the memory cell transistorM is as follows: the threshold voltage is −2V when data “1” has beenstored, the threshold voltage is 1V when data “2” has been stored, thethreshold voltage is 2V when data “3” has been stored, and the thresholdvoltage is 3V when data “4” has been stored.

[0306] In this case, when data is read, voltage of 3V appears at the bitline BL when the memory cell transistor M2 has stored data “1”, voltageof 2V appears when the same has stored data “2”, voltage of 1V appearswhen the same has stored data “3” and voltage of 0V appears when thesame has stored data “4”, as shown in FIG. 5.

[0307]FIG. 6 is a diagram showing a state where voltage is applied whendata is written in the NAND cell shown in FIGS. 3A and 3B.

[0308] Data is written such that voltage corresponding data as shown inFIG. 6 is applied to the bit line BL to raise the voltage of each of theselection gate SG1 and control gates CG1 and CG3 to CG4 to 10V, that ofthe selected control gate CG2 to 20V and that of each of the controlgate SG2 and the common source line VS to be 0V. The bit line BL isapplied with voltage corresponding to data to be written such that 8V isapplied when data “1” is written, 2V is applied when data “2” iswritten, 1V is applied when data “3” is written and 0V is applied whendata “4” is written.

[0309] When data “4” is written, the difference of the potential betweenthe control gate CG of the memory cell transistor M and the channel ofthe same is increased to 20V so that the well-known tunnel currentcauses electrons to be injected from the channel into the floating gateso that the threshold voltage of the memory cell transistor M isconsiderably shifted in a direction toward positive-levels. As a result,the threshold voltage of the memory cell transistor M is made to be, forexample, 3V. When data “3” is written or when data “2” is written, thedifference in the potential between the control gate CG2 and the channelis made to be smaller as compared with the difference in the potentialwhen Data “4” is written. Therefore, the quantity of electrons to beinjected into the floating gate is reduced. Thus, the threshold voltageis made to be, for example, 2V and 1V.

[0310] When data “1” is written, the difference in the potential betweenthe control gate CG2 and the channel is made to be a low voltage of 12V.In this case, any tunnel current does not flow, thus causing thethreshold voltage of the memory cell transistor M to be maintained inthe state where data has been erased.

[0311] Data is erased by making the voltage of each of the control gateCG1 to CG4 to be 0V, while the p-type well or the p-type substrate isapplied with 20V. As a result, a tunnel current flows in a directionopposite to the direction when data is written. As a result, electronsare discharged from the floating gate to the p-type well or the p-typesubstrate. An example of the threshold voltage of the memory celltransistor M in the state where data has been erased is, for example,−2V.

[0312] The details of a data circuit 6 shown in FIG. 2 will now bedescribed with reference to FIG. 7. FIG. 7 shows the structure in a casewhere four-level data is stored.

[0313] As shown in-FIG. 7, the data circuit 6 has first 5 and secondsense amplifiers 6A1 and 6A2 for detecting data in the memory celltransistor appeared on the bit line BL so as to amplify above data,first and second data latches 6B1 and 6B2 for storing data to be writtenin the memory cell transistor, and first and second verify circuits 6C1and 6C2 for detecting whether or not writing into the cell has beenperformed sufficiently in accordance with data detected by the first andsecond sense amplifiers 6A1 and 6A2 and data stored in the first andsecond data latches 6B1 and 6B2 at the time of verification to generatedata to be written next so as to transfer generated data to the firstand second data latches 6B1 and 6B2. Moreover, the data circuit 6 has awrite circuit 6D for supplying data, to be written into the cell, to thebit line BL as voltage in accordance with the cell of the first andsecond data latches 6B1 and 6B2.

[0314] One-bit data is communicated between outside of the chip and thedata circuit 6 through first and second data input/output linesrespectively so that data in a quantity of two bits is communicated.

[0315] Data is read from the first and second sense amplifiers 6A1 and6A2 to the outside of the chip, through the corresponding first andsecond data input/output lines. When a writing operation is performed,data is supplied from the outside of the chip to the first and seconddata latches 6B1 and 6B2 through the first and second data input/outputlines.

[0316] The sense amplifier 6A1 is supplied with second reference voltageserving as reference voltage for detecting data. The sense amplifier 6A2is supplied with either the first reference voltage or the thirdreference voltage-which is selectively switched in accordance with thecontent of the sense amplifier 6A1 or the first data latch 6B1.

[0317] The operation will now be described.

[0318] Initially, a reading operation will now be described.

[0319] Any one of four-level data “1”, “2”, “3” or “4” is read from thememory cell transistor M selected by the word line (the control gate).In accordance with read four-level data, any one of voltages 3V, 2V, 1Vor 0V appears at the bit line BL. Read data which has appeared at thebit line BL is supplied to both of the first and second sense amplifiers6A1 and 6A2.

[0320] Initially, the sense amplifier 6A1 is operated. The senseamplifier 6A1 is supplied with the second reference voltage (=1.5V) asthe reference voltage. Read data is compared with the second referencevoltage by the sense amplifier 6A1. If read data is “1” or “2”, thevoltage is higher than the second reference voltage. Therefore, thesense amplifier 6A1 detects “H” level and amplifies the same.

[0321] If data is “3” or “4”, the voltage is lower than the secondreference voltage. Therefore, the sense amplifier 6A1 detects “L” leveland amplifies the same.

[0322] Then, the sense amplifier 6A2 is operated.

[0323] If the output from the sense amplifier 6A1 is “H”, then the senseamplifier 6A2 is supplied with the first reference voltage (=2.5V) asthe reference voltage. If data is “1”, the voltage is higher than thefirst reference voltage, the sense amplifier 6A2 detects “H” level andamplifiers the same. If data is “2”, the voltage is lower than the firstreference voltage. Therefore, the sense amplifier 6A2 detects “L” andamplifies the same.

[0324] If the output from the sense amplifier 6A1 is “L”, the senseamplifier 6A2 is supplied with the third reference voltage (=0.5V) asthe reference voltage. If data is “3”, the voltage is higher than thethird reference voltage. Therefore, the sense amplifier 6A2 detects “H”and amplifies the same. If data is “4”, the voltage is lower than thethird reference voltage. Therefore, the sense amplifier 6A2 detects “L”and amplifies the same.

[0325] As described above, the four-level data “1”, “2”, “3” and “4”expressed as the voltage levels on one bit line BL are expressed by twobits as “H, H”, “H, L”, “L, H” and “L, L” in accordance with the outputlevel from the sense amplifier 6A1 and that from the sense amplifier6A2. Thus, four-level data which has appeared on one bit line BL isconverted into two-bit binary data. Two-bit binary data is read to theoutside of the chip through the first and second data input/outputlines.

[0326] Then, a writing operation will now be described.

[0327] Two-bit binary data is, through first and second datainput/output lines, supplied to the first and second data latches 6B1and 6B2. Then, the contents of the first and second data latches 6B1 and6B2 are supplied to the write circuit 6D.

[0328]FIG. 8 is a circuit diagram showing an example of the writecircuit 6D.

[0329] In synchronization with write signal WRT, the write circuit shownin FIG. 8 applies, to the bit line BL, four-level data “1”=8V, “2”=2V,“3”=1V and “4”=0V to correspond to the output levels from the first datalatch 6B1 and the data latch 6B2 to correspond to two-bit data “L, L”,“L, H”, “H, L” and “H, H”.

[0330] High voltage of, for example, 20V is applied to the selected wordline. In accordance with the voltage of the bit line BL, electrons areinjected into the floating gate so that writing proceeds. If data is“1”, injection of electrons is not performed and thus the thresholdvoltage of the cell is not changed.

[0331] In order to accurately write data, that is, in order todistribute threshold voltages in a narrowest voltage range, a verifyingoperation is performed after data has been written. The foregoingoperation is repeatedly performed. In order to improve the accuracy,verification is performed for each bit to enable data to be writtenoptimally in each bit.

[0332] The verifying operation will now be described.

[0333] Initially, the bit line BL is reset to 0V similarly to thereading operation. Then, the voltage of the column selection line ismade to be 3V, and the word line (the control gate) is also applied with3V. If a margin is given to the threshold voltage after data has beenwritten, it is preferable that the voltage of the word line (the controlgate) is set to be a slightly lower level as compared with that whendata is read, for example, 2.8V.

[0334] Voltage corresponding to the writing operation appears at the bitline BL so as to be applied to the first and second sense amplifiers 6A1and 6A2. When the verifying operation is performed, the sense amplifier6A2 is first operated. Whether the first reference voltage is applied tothe sense amplifier 6A2 or the third reference voltage is applied to thesame is determined in accordance with the content of first data latch6B1. If the output from the first data latch 6B1 is “L”, the data latch6B2 is supplied with the first reference voltage (=2.5V). If the outputfrom the data latch 6B2 is “H”, the third reference voltage (=0.5V) isapplied to the sense amplifier 6A2.

[0335] Then, the sense amplifier 6A2 is operated.

[0336] If the content of the data latch 6B2 is “H”, that is, write datais “2” or “4”, the sense amplifier 6A2 makes a reference to the firstreference voltage or the third reference voltage similarly to thereading operation to detect the voltage of the bit line BL and amplifiesthe voltage. If the output from the sense amplifier 6A2 is “H”, it isdetermined that writing of data “2” or “4” is insufficient. In thiscase, the sense amplifier 6A1 is not operated but the writing operationis again performed. If the output from the sense amplifier 6A2 is “L”,it is determined that writing of data “2” or “4” has been performedsufficiently.

[0337] If the content of the data latch 6B2 is “L”, that is, if thewrite data is “1” or “3”, the output from the sense amplifier 6A2 isforcibly made to be “L”.

[0338] When the output from the sense amplifier 6A2 is forcibly made tobe “L”, determination of the degree of writing of data “3” is notperformed. To overcome this, the sense amplifier 6A1 is then operated.

[0339] If the content of the first data latch 6B1 is “H”, that is, writedata is “3” or “4”, the sense amplifier 6A1 makes a reference to thesecond reference voltage similarly to the reading operation to detectthe voltage of the bit line BL and amplifies the same. If the outputfrom the sense amplifier 6A1 is made to be “H”, it is determined thatwriting of data “3” is insufficient. In this case, the writing operationis again performed. If the output from the sense amplifier 6A1 is “L”, adetermination that writing of data “3” has been performed sufficientlyis performed.

[0340] If the content of first data latch 6B1 is “L”, that is, if writedata is “1” or “2”, the output from the sense amplifier 6A1 is forciblymade to be “L”.

[0341] If a determination has been performed that writing of data “2”,“3” or “4” is insufficient, two-bit data “L, H”, “H, L” and “H, H”,which are the same as those before writing are stored by the first datalatch 6B1 and the data latch 6B2. When next writing is performed, awriting operation similar to the previous operation is performed.

[0342] If data “1” is written, that is, if the threshold voltage of thememory cell transistor is not changed and if determination is performedthat writing of data “2”, “3” or “4” has been sufficiently written, data“L, L” is stored in the first data latch 6B1 and second data latch 6B2to prevent change of the threshold voltage when next writing isperformed.

[0343] Each of the writing operation and the verifying operation issimultaneously performed for a plurality of memory cells. If a memorycell to which data has been written insufficiently exists, writing andverification are repeatedly performed. When writing to all of the memorycells has been completed (when writing has been performed sufficiently),the write completion detecting circuit 18 detects the completion andinterrupts the writing operation. If a memory cell, to which data hasnot been sufficiently written, exists even after the writing orverifying operation has been repeated by a predetermined number oftimes, it is determined that writing bas been failure and the writingoperation is ended.

[0344] The multilevel storing NAND type EEPROM having the verifyingmeans for each bit according to the first embodiment is able to limitthe number of each of the data latching circuits, the sense amplifiersand the verifying circuits to “m” when it is assumed that the number ofthe multilevel data is “n” (n=2^(m) and m=log₂n (m is a natural numbernot smaller than 2)). Therefore, if it is assumed that the number ofmultilevel data items is “n”, the conventional structure requires (n−1)data latch circuits, sense amplifiers and verifying circuits. However,the present invention is able to considerably-reduce the number of theforegoing circuits.

[0345] Specifically, if it is assumed that the number of multilevel dataitems is 4, the conventional apparatus requires 4−1=3 sets of data latchcircuits, sense amplifiers and verifying circuits. However, theapparatus according to the first embodiment is able to reduce the numberto log₂4=2 sets. Therefore, the size of the column-system circuit can bereduced because the number of the sense amplifiers and the senseamplifiers can be decreased. As a result, a highly integrated circuitcan be realized.

[0346] Moreover, the number “m” of the data latch circuits and the senseamplifiers can be made to be the same as the number of bits of the datainput/output lines to be connected to the data latch circuits and thesense amplifiers. At this time, one bit data is assigned to each of “m”data latch circuits and sense amplifiers. As a result, the structure ofthe circuit can be simplified. Since the simplified circuit structurerealizes a basic component of a multilevel storing semiconductor memorydevice, the function and performance can be improved.

[0347] It is preferable that “m” data latch circuits and senseamplifiers be assigned in the descending order from the first data bitto the m-th bit which is the least significant bit. When the foregoingstructure is employed, data is read from the memory cell transistor suchthat the operation is started at the first data latch/sense amplifiertoward the m-th data latch/sense amplifier assigned to the leastsignificant m-th bit. The foregoing structure attains an effect that thenumbers of the data latches and sense amplifiers can easily be increasedwhen the number of bits is sequentially increased as, for example, “3”,“4”, to correspond to the increase.

[0348] In the above-mentioned embodiment, the number of bits is “2”.Thus, the first data latch 6B1 and the sense amplifier 6A1 assigned tothe first bit which is the most significant bit, subject read data to acomparison with the second reference voltage. A result of the comparisonrepresenting whether read data is higher or lower than the secondreference voltage is initially output. In accordance with the aboveoutput, the level of the reference voltage to be applied to the datalatch 6B2 and the sense amplifier 6A2 assigned to the second bit isswitched to the first or third reference voltage to output a result of acomparison representing whether the read data is higher than the firstreference voltage or the third reference voltage. As described above,each data item of four-level data respectively are identified andfour-level data is converted into two-bit data.

[0349] When the number of bits has been increased to “3”, a basicstructure is employed in which the operation is performed from the mostsignificant bit to the least significant bit. Initially, read data issubjected to a comparison with the fourth reference voltage by the firstdata latch/sense amplifier assigned to the first bit, which is the mostsignificant bit. Then, a result of the comparison representing whetheror not read data is higher than the fourth reference voltage is output.In accordance with the output, the level of the reference voltage to beapplied to the second data latch/sense amplifier assigned to the secondbit, which is the next bit, is switched to the second reference voltageor the sixth reference voltage. A result of a comparison representingwhether read data is higher or lower than the second reference voltageor the fourth reference voltage is output. In accordance with theoutput, the level of the reference voltage to be applied to the thirddata latch/sense amplifier assigned to the third bit, which is the nextbit, is switched to any one of the first reference voltage, the thirdreference voltage, the fifth reference voltage or the seventh referencevoltage. As a result, eight-level data can be identified and 8-leveldata can be converted into 3-bit data.

[0350] When data is read from the memory cell to perform verification,“m” data latches and sense amplifiers are operated such that theoperation proceeds from the m-th data latch/sense amplifier assigned tothe m-th bit, which is the least significant bit, toward the first bit,which is the most significant bit. The foregoing structure realizes thestructure of a circuit capable of protecting data for setting thereference voltage, that is, write data, from being destroyed by theverifying operation. Therefore, a result of the verification can bedetermined by using the data latch and the sense amplifier which arelatching the same write data item.

[0351] Moreover, m-bit and n-level read data and m-bit and n-level writedata are given by different data items. As a result, a structure can beprovided in which comparison of write data latched by the data latch andthe sense amplifier with read data enables a result of the verificationto be detected.

[0352] A method of determining a result of validity determination of theverification by the structure according to this embodiment will brieflybe described. Write data and read data latched by the data latch and thesense amplifier are subjected to a comparison. If write data is changedby the read data, it is determined that the result of the verificationis valid.

[0353] Moreover, the above-mentioned embodiment has a structure suchthat the verifying circuit is controlled to be turned on or off withwrite data latched by the data latch and the sense amplifier. As aresult, an effect can be obtained in that the size of a circuit forcontrolling the verifying circuit can be reduced. Moreover, theverifying circuit can be turned off immediately after write data latchedby the data latch and the sense amplifier has been changed. Therefore,the verifying circuit can precisely be controlled and thus the operationspeed of the verifying circuit can be raised. Thus, possibility ofoverwriting caused from, for example, slow operation of the verifyingcircuit can-be lowered.

[0354] When the embodiment having the above-mentioned structure isformed such that the number of bits of the data input/output lines, thenumber of bits of write data to be supplied from outside of theapparatus to the inside portion of the apparatus and the number of bitsof read data to be output from the apparatus to the outside ofthe-apparatus are made to be the same, a structure can be realized withwhich a circuit for converting the number of bits can be omitted. If thecircuit for converting the number of bits can be omitted, both of higherintegration and high speed input/output operation can be achieved.

[0355] The foregoing structure can as well as be achieved by anarrangement in which the circuit for converting the number of bits isformed into a precise structure capable of operating at high speed.However, a structure for realizing a further precise circuit forconverting the number of bits capable of operating at higher speedencounters a problem of noise generated in the integrated circuit. Ifthe circuit for converting the number of bits is affected by noiseabove, there arises a risk that data can erroneously be converted. Thatis, there arises a risk that the satisfactory reliability of the presentcircuit for converting the number of bits deteriorates. In view of theforegoing, it is preferable that the circuit for converting the numberof bits be omitted from the structure in the future. The NAND typeEEPROM according to this embodiment has a structure with which thecircuit for converting the number of bits can be omitted.

[0356] The above-mentioned embodiment may be modified such that thenumber of bits of write data is not converted and supplied from outsideof the apparatus into the data latch and the sense amplifier. Moreover,the number of bits of read data is not converted and output to theoutside of the apparatus. As a result of employment of theabove-mentioned structure, a multilevel storing NAND type EEPROM can beobtained which is capable of realizing high degree of integration andhigh speed input/output operation with satisfactory reliability.

[0357] Other embodiments of the present invention will now be described.Elements in the following embodiments which are the same as thoseaccording to the first embodiment are given the same reference numeralsand the same elements are omitted from detailed description.

[0358] (Second Embodiment)

[0359] A second embodiment of the present invention will now bedescribed in which the structure of the bit line controller 3C ismodified.

[0360]FIG. 9 is a diagram showing the structure of a NAND type EEPROMaccording to the second embodiment. FIG. 10 is a circuit diagram showingbit line controller 3D shown in FIG. 9. FIG. 11 is a circuit diagramshowing a flip-flop circuit 14-1 shown in FIG. 10. FIG. 12 is a circuitdiagram showing the flip-flop circuit 14-2 shown in FIG. 10.

[0361] As shown in FIG. 9, the bit line controller 3D established theconnection between a two-bit (data input/output lines I/OA and I/OB forma one bit line and data input/output lines I/OC and I/OD form a one bitline) data input/output line I/O and a bit line BL. Moreover, a columngate circuit 12 having a gate for receiving column selection signal CSLis connected between a data circuit 6E and the data input/output lineI/O in the bit line controller 3D. The data circuit 6E is connected tothe data input/output line I/O when it is selected in response to thecolumn selection signal CSL. A transfer gate circuit 7 having a gate forreceiving transfer gate drive signal BLC is connected between the datacircuit 6E and the bit line BL. The data circuit 6E is connected to thebit line BL when the transfer gate drive signal BLC is “H” level.

[0362] As shown in FIG. 10, the data circuit 6E includes two flip-flopcircuits 14-1 and 14-2. The first flip-flop circuit 14-1 has two nodesVL1-1 and VL2-1. The nodes VL1-2 and VL2-1 respectively are connected tothe data input/output lines I/OB-and I/OA. Similarly, the secondflip-flop circuit 14-2 has two nodes VL1-2 and VL2-2. The nodes VL1-2and VL2-2 respectively are connected to the data input/output lines I/ODand I/OC.

[0363] As shown in FIGS. 11 and 12, each of the flip-flop circuits 14-1and 14-2 is formed of transistors Q1-1 to Q6-1 and Q1-2 to Q6-2.

[0364] The flip-flop circuit 14-1 forms the first data latch 6B1 andsense amplifier 6A1 shown in FIG. 7 so that the flip-flop circuit 14-1serves as the sense amplifier 6A1 when data is read and as the datalatch 6B1 when data is written. Similarly, the flip-flop circuit 14-2form the data latch 6B2 and the sense amplifier 6A2 shown in FIG. 7.When data is read, the flip-flop circuit 14-2 serves as the senseamplifier 6A2. When data is written, the flip-flop circuit 14-2 servesas the data latch 6B2.

[0365] The first node VL1-1 of the flip-flop circuit 14-1 is connectedto a node N2-1 of the data circuit 6E through a transistor Q7-1 having agate for receiving drive signal RV1 and a transistor Q9-1 having a gatefor receiving drive signal LH1. The node N2-1 is supplied with secondreference voltage Vref2. The second node VL2-1 of the flip-flop circuit14-1 is connected to a node N1 of the data circuit 6E through atransistor Q8-1 having a gate for receiving the drive signal RV1 and atransistor Q10-1 having a gate for receiving the drive signal LH1. Thenode N1 is connected to the bit line BL through the transfer gatecircuit 7.

[0366] The first node VL1-2 of the flip-flop circuit 14-2 is connectedto node N2-2 of the data circuit 6E through a transistor Q7-2 having agate for receiving the drive signal RV2 and a transistor Q9-2 having agate for receiving the drive signal LH2. The node N2-2 is supplied withfirst reference voltage Vref1 or third reference voltage Vref3. Thesecond node VL2-2 of the flip-flop circuit 14-2 is connected to a nodeN1 of the data circuit 6E through a transistor Q8-2 having a gate forreceiving the drive signal RV2 and a transistor Q10-2 having a gate forreceiving the drive signal LH2.

[0367] A first verifying circuit 16-1 is connected between a node VN2-1between the transistor Q8-1 and the transistor Q10-land a node VL1-1.The first verifying circuit 16-1 includes a transistor Q11-1 having agate for receiving a verifying signal VRFY1 and a transistor Q12-1having a gate connected to the node VL1-1. The transistor Q11-1 and thetransistor Q12-1 are, in series, connected to each other and areconnected between a low-potential power source (ground potential Vss)and the node VN2-1.

[0368] A second verifying circuit 16-2 is connected between the nodeVN2-2 between the transistor Q8-2 and the transistor Q10-2 and the nodeVL1-2. The second verifying circuit 16-2 includes a transistor Q11-2having a gate for receiving verifying signal VRFY2 and a transistorQ12-2 having a gate connected to the node VL1-2. The transistor Q11-2and the transistor Q12-2 are, in series, connected to each other andconnected between the lower potential power source (ground potentialVss) and the node VN2-2.

[0369] The operation will now be described.

[0370]FIG. 13 is a waveform showing the operation which is performedwhen data is read.

[0371] When data is read, the flip-flop circuits 14-1 and 14-2respectively act as sense amplifiers. Prior to reading data, the nodesVL1-1, VL2-1, VL1-2, VL2-2, VN1-1, VN2-1, VN1-2 and VN2-2 of theflip-flop circuits 14-1 and 14-2 are initialized to a voltage levelbetween the power source potential Vcc and the ground voltage Vss. Notethat the initializing circuit is omitted from illustration. One wordline defined in accordance with a supplied address signal is activatedso that data is output from a selected memory cell transistor to the bitline BL so that the bit line BL is electrically charged. The bit line ischarged with 3V when data “1” has been output, 2V when data “2” has beenoutput, 1V when data “3” has been output and 0V when data “4” has beenoutput.

[0372] The flip-flop circuit 14-1 is applied with 1.5V as the secondreference voltage Vref2. The flip-flop circuit 14-2 is applied witheither 0.5V as the first reference voltage Vref1 or 2.5V as the thirdreference voltage Vref3. The first reference voltage Vref1 and the thirdreference voltage Vref3 are switched in accordance with a result of thedetection performed by the flip-flop circuit 14-1, as described in thefirst embodiment. Note that the selector is omitted from illustration.

[0373] The level of the drive signal LH1 is raised to “H” level at asimilar timing as that of the word line so that the voltage of the bitline BL is transferred to the nodes VN2-1 and VL2-1. The secondreference voltage Vref2 is transferred to the nodes VN1-1 and VL1-1.When the transfer has been completed, the level of the drive signal LH1is lowered to “L” level so that the flip-flop circuit 14-1 is separatedfrom the bit line and the second reference voltage Vref2. Then,sense-amplifier activating signal SAN1 and (reverse) SAP1 are suppliedto activate the flip-flop circuit 14-1 so that a data sense-amplifyingoperation is started. As a result, the voltage of the bit line BLtransmitted to the node VL2-1 and the second reference voltage Vref2transmitted to the node VL1-1 are subjected to a comparison. Thus, thestates of the nodes VL1-1 and VL2-1 are determined to be either “H, L”or “L, H”.

[0374] Then, based on the result of detection performed by the flip-flopcircuit 14-1, the first reference voltage Vref1 and the third referencevoltage Vref3 are switched.

[0375] Then, the flip-flop circuit 14-2 is operated. Initially, thelevel of the drive signal LH2 is raised to “H” level similarly to theforegoing operation so that the voltage of the bit line BL istransmitted to the nodes VN2-2 and VL2-2. When each transfer has beencompleted, the level of the drive signal LH2 is lowered to “L” level sothat the flip-flop circuit 14-2 is separated from the bit line BL andreference voltage Vref1 or Vref3. Then, sense-amplifier activatingsignal SAN2 and (reverse) SAP2 are supplied so that the flip-flopcircuit 14-2 is activated and the operation for sense-amplifying readdata is started. As a result, the voltage of the bit line BL transmittedto the node VL2-2 and the reference voltage Vref1 or Vref3 transmittedto the node VL1-2 are subjected to a comparison. Thus, the states of thenodes VL1-2 and VL2-2 are determined to be either “H, L” or “L, H”.

[0376]FIG. 15 is a table showing the states of the nodes VL1-1, VL2-1,VL1-2 and VL2-2 of the sense amplifier (the flip-flop) after four-leveldata has been read. As shown in FIG. 15, read data is transferred to thedata input/output circuit 5 through the data input/output line I/O so asto be read to the outside of the chip.

[0377]FIG. 14 is a waveform showing the operation which is performedwhen data is written.

[0378] When data is written, the flip-flop circuits 14-1 and 14-2respectively act as data latches. Similarly, data supplied from outsideof the chip to the data circuit 6E is transferred to the nodes VL1-1,VL2-1, VL1-2 and VL2-2 through the data input/output line I/O.

[0379]FIG. 16 is a table showing states of nodes VL1-1, VL2-1, VL1-2 andVL2-2 when four-level data is written. Data supplied to the nodes VL1-1,VL2-1, VL1-2 and VL2-2 is transferred to the writing circuit shown inFIG. 8 so that voltage corresponding to above data, for example, 8V, 2V,1V and 0V to the bit line BL. Then, the foregoing write voltage isapplied to the memory cell transistor selected in response to theaddress signal so that data is written in the memory cell transistor. Inorder to narrow the distribution of the threshold voltage of the memorycell transistor after data has been reference numeral, writing isrepeatedly performed in each small quantity. Moreover, the verifyingoperation is performed between the writing operations.

[0380] The verifying operation is performed similarly to the readingoperation except for an operation for modifying the voltage of the bitline BL transferred to the nodes VN2-1 and VN2-2 in accordance withwrite data latched by the flip-flop circuits 14-1 and 14-2.

[0381] Referring to FIG. 10, the verifying operation will now bedescribed.

[0382] The flip-flop circuits 14-1 and 14-2 have latched write data.Prior to performing the verifying operation, the level of the each ofthe drive signals RV1 and RV2 is lowered to a low voltage level so as tomake non-conductive the transistors Q7-1, Q7-2, Q8-1 and Q8-2 so as toseparate the node VL1-1 and the node VN1-1 from each other, the nodeVL1-2 and the node VN1-2 from each other, the node VL2-1 and the nodeVN2-1 from each other, and the node VL2-2 and the node VN2-2 from eachother.

[0383] Then, similarly to the reading operation, the word line isactivated so that data is output from the selected memory celltransistor to the bit line BL. For example, 3V is charged to the bitline BL when data “1” has been output, 2V is charged when data “2” hasbeen output, 1V is charged when data “3” has been output and 0V ischarged when data “4” has been output. The reference voltage Vref2 to besupplied to the flip-flop circuit 14-1 is 1.5V. On the other hand, theflip-flop circuit 14-2 is supplied with either 0.5V as the referencevoltage Vref1 or 2.5V as the reference voltage Vref3 in accordance withdata latched by the flip-flop circuit 14-1. When data in the nodes VL1-1and VL1-2 is “H, L”, Vref3 is applied. When data in the nodes VL1-1 andVL1-2 is “L, H”, Vref1 is applied.

[0384] At a similar timing to that of the word line, the level of thedrive signal LH2 is raised to “H” level so that the voltage of the bitline BL is transmitted to the node VN2-2 and either the referencevoltage Vref1 or Vref3 is transmitted to the node VN1-2. After eachtransfer has been completed, the level of the signal LH2 is lowered to“L” level so that the flip-flop circuit 14-2 is separated from the bitline BL and the reference voltage Vref1 or Vref3.

[0385] Then verify signal VRFY2 is supplied to modify the voltage outputto the node VN2-2 in accordance with latched data. Therefore, the levelof the verify signal VRFY2 is raised to high voltage to make conductivethe transistor Q11-2. If data latched by the nodes VL1-2 and VL2-2 is“H, L” at this time, also the transistor Q12-2 is made conductive sothat the node VN2-2 is electrically discharged to the ground voltage. Ifdata l to the nodes VL1-2 and VL2-2 is “L, H”, the transistor Q12-2 isnon-conductive and the voltage of the node VN2-2 transferred from thebit line BL is not changed.

[0386] Then, sense-amplifying activating signal SAN2 and (reverse) SAP2are supplied to activate the flip-flop circuit 14-2 so as to start theoperation for sensing and amplifying read data. As a result, the voltageof the bit line BL transmitted to the node VL1-2 and the referencevoltage Vref1 or Vref3 transmitted to the node VL1-1 are subjected to acomparison so that the states of the nodes VL1-2 and VL2-2 aredetermined to be either “H, L” or “L, H”. The foregoing states arelatched as data to be written next.

[0387] If the states of the nodes VL1-2 and VL2-2 of the flip-flopcircuit 14-2 is “H, L” after the sensing operation has been completed ina state where the reference voltage is 2.5V (Vref3), it means that writedata is “1” or “2” and required writing has been performed.

[0388] Then, operation is shifted to the operation of the flip-flopcircuit 14-1. Since the node VL1-1 of the flip-flop circuit 14-1 is “H”level, the node VN2-1 is electrically discharged to the ground voltagewhen the verifying signal VRFY1 has been supplied. Therefore, after theoperation has been started, the flip-flop circuit 14-1 is brought to astate in which the nodes VL1-L and VL2-1 are “H, L”. Thus, it isdetermined that writing of write data “1” (since writing is notperformed when data is “1”, no comparison between read data and thereference voltage Vref2 is performed and completion of written isdetermined) and write data “2” have been completed. At this time, datain the flip-flop circuits 14-1 and 14-2 is made to be “H, L” for all ofthe nodes VL1-1, VL2-1, VL1-2 and VL2-2.

[0389] When the state of the flip-flop circuit 14-2 is such that thenodes VL1-2 and VL2-2 are “L, H” after the sensing operation has beenperformed in a state where the reference voltage is 2.5V (Vref3), it isdetermined that write data “2” has not been written as desired. At thistime, the flip-flop circuit 14-1 is not operated. Therefore, the nodesVL1-1 and VL2-1 of the flip-flop circuit 14-1 are maintained in “H, L”before the verification and the operation is shifted a next writingoperation.

[0390] At this time, the states of the flip-flop circuits 14-1 and 14-2are such that the nodes VL1-1 and VL2-1 are “H, L” and the nodes VL1-2and VL2-2 are “L, H” so that data is the same as that before the writingoperation.

[0391] If the state of the flip-flop circuit 14-2 is “H, L” after thesensing operation has been completed in a state where the referencevoltage is 0.5V (Vref1), it means a fact that write data “3” or “4” hasbeen written as desired.

[0392] Then, the operation is shifted to the operation of the flip-flopcircuit 14-1. Since the node VL1-1 of the flip-flop circuit 14-1 is “L”,the transistor Q12-1 is non-conductive even if the signal VRFY1 issupplied. Therefore, the voltage of the node VN2-1 is not changed andthe voltage transferred from the bit line is maintained. Then, the senseamplifying activation signal SAN1 and (reverse) SAP1 are supplied sothat the sense amplifying operation is started. Data transmitted to thenodes VL2-1 and VL1-1 and the reference voltage Vref2 are subjected to acomparison so that the state of the nodes VL1-1 and VL2-1 is determinedto be either “H, L” or “L, H”. The state is latched as data to bewritten next.

[0393] When write data is “3” and data in the nodes VL1-1 and VL2-1 ofthe flip-flop circuit 14-1 is “H, L”, it means a fact that requiredwriting corresponding to data “3” has been performed. In the nextrewriting cycle, no writing is performed. Then, data “H, L” in the nodesVL1-1 and VL2-1 and the nodes VL1-2 and VL2-2 is set to the flip-flopcircuits 14-1 and 14-2. When data in the nods VL1-1 and VL2-1 of theflip-flop circuit 14-1 is “L, H”, it means a fact that writingcorresponding to data “3” is insufficient. Therefore, data “3” iswritten in the next rewriting cycle by setting data “L, H” in the nodeVL1-1 and VL2-1 and data “H, L” in the nodes VL1-2 and VL2-2 which arethe same as those before writing to the flip-flop circuits 14-1 and14-2.

[0394] When the state of the flip-flop circuit 14-2 is “L, H”, it meansa fact that write data is “4” and writing is insufficient. At this time,the flip-flop circuit 14-1 is not operated and data in the flip-flopcircuits 14-1 and 14-2 is maintained at data in the nodes VL1-1 andVL2-1, that is, data (=“L, H”) in the nodes VL1-2 and VL2-2. Then, shiftto the writing operation is again performed.

[0395]FIG. 17 is a table showing states of the nodes VL1-1, VL2-1, VL1-2and VL2-2 during verification of four-level data.

[0396] The foregoing operation loop consisting of writing of data,verification reading of data, and data writing operation is repeateduntil data is sufficiently written in all of the selected memory celltransistors. If cell, to which data has not been satisfactorily written,exists, the chip is determined to be a defective chip and the writingoperation is ended.

[0397] If data has sufficiently be written in the memory cell, data ofboth of the flip-flop circuits 14-1 and 14-2 is made to be data in thenodes VL1-1 and VL2-1, that is, data in nodes VL1-2 and VL2-2, that is,“H, L”. Thus, a writing completion signal is supplied to the writecompletion detecting circuit 18 to complete the writing operation.

[0398] If a cell, to which data has not been sufficiently written,exists after writing has been repeated by a predetermined number oftimes, a circuit (not shown) for counting the number of writing timestransmits a signal denoting this to the detection circuit. Then, thewrite completion detecting circuit 18 generates a write error signal sothat the writing operation is ended.

[0399] (Third Embodiment)

[0400]FIG. 18 is a diagram showing structures of a memory cell array 1and a column-system circuit 3 of an EEPROM according to a thirdembodiment of the present invention.

[0401] In the first and second embodiment has the structure in which onedata circuit 6 corresponds to one bit line BL. In the present invention,a modification is permitted such that one data circuit 6 corresponds toa plurality of the bit lines BL. This modification is the thirdembodiment.

[0402] As shown in FIG. 18, the EEPROM according to the third embodimenthas a structure such that one of data circuits 6-0 to 6-m is providedfor four bit lines BL1-1 to BLi-4 (i is any one of 0 to m). When, forexample, BLi-1 is selected from four bit lines BLi-1 to BLi-4, the levelof signal BLC1 among drive signals BLC1 to BLC4 for driving a transfergate circuit 7B for the data circuit is raised to “H” level. On theother hand, the level of other signals BLC2 to BLC4 is made to be “L”level.

[0403] Simultaneously, the level of signal BLC1D among drive signalsBLC1D to BLC4D for driving a transfer gate 7A of a non-selection bitline controller 20 is made to be “L” level. On the other hand, the levelof the other drive signals BLC2D to BLC4D is made to be “H” level. As aresult, only the selected bit line BLi-1 is connected to the datacircuits 6-0 to 6-m.

[0404] Thus, only selected bit line BLi-1 is connected to the datacircuits 6-0 to 6-m, while non-selected bit lines BLi-2 to BLi-4respectively connected to the non-selected bit line controllers 20-0 to20-m. The non-selected bit line controllers 20-0 to 20-m controlpotentials of the non-selected bit lines BLi-2 to BLi-4.

[0405] (Fourth Embodiment)

[0406]FIG. 19 is a diagram showing the structure of a multilevel storingNAND type EEPROM according to a fourth embodiment of the presentinvention.

[0407] As shown in FIG. 19, the multilevel storing NAND type EEPROMaccording to the fourth embodiment has a structure called an open bitstructure. The open bit type multilevel storing NAND type EEPROM hasmemory cell arrays 101-1 and 101-2 having memory cells arranged in amatrix manner, row-system circuits 102-1 and 102-2 provided tocorrespond to the memory cell arrays 101-1 and 101-2 and a column-systemcircuit 103 arranged to be commonly used by the memory cell arrays 101-1and 101-2.

[0408] The row-system circuits 102-1 and 102-2 have a row decoder 102Afor receiving an address signal output from an address input circuit(buffer) 104 to select a row in a memory cell array in accordance withthe supplied address signal, and a word line driver 102B for driving aword line of memory cell arrays 101-1 and 101-2 in accordance with anoutput from a row decoder 102A. In the case of the NAND type EEPROM, theword lines are selection gates SG (SGA and SGB) and control gates CG(CGA and CGB). The word line driver 102B is also called a controlgate/selection gate driver.

[0409] The column-system circuit 103 which is commonly used by thememory cell arrays 101-1 and 101-2 has a column decoder 103A forreceiving the address signal output from the address buffer 104 toselect a column in the memory cell arrays 101-1 and 101-2 in response tothe supplied address signal, and a column selection line driver 103B fordriving a column selection line for selecting a column of the memorycell arrays 101-1 and 101-2 in accordance with an output from the columndecoder 103A.

[0410] Moreover, the column-system circuit 103 has a bit line controller103C including a data circuit for temporarily storing data to be writtenin the memory cell and reading data in the memory cell.

[0411] The bit line controller 103C is connected to a data input/outputcircuit (data input/output buffer) 105 through an data input/output lineI/O. Moreover, the bit line controller 103C is, through a bit line BLa,connected to memory cells of the memory cell array 101-1 and memorycells of the memory cell array 101-2.

[0412] The bit line controller 103C receives write data from the datainput/output buffer 105 when data is written to output received writedata to the memory cell arrays 101-1 and 101-2. The bit line controller103C receives read data from the memory cell when data is read to outputthe supplied read data to the data input/output buffer 105.

[0413] The data input/output buffer 105 controls input and output ofdata such that it introduces write data supplied from outside of theEEPROM to a memory core portion and outputs data read from the memorycore portion to the outside of the EEPROM.

[0414] The write completion detecting circuit 118 detects whether or notwriting of data has been completed in accordance with an output from thebit line controller.

[0415]FIG. 20 is a diagram showing the structures of the memory cellarray and the column-system circuit shown in FIG. 19.

[0416] As shown in FIG. 20, each of the memory cell arrays 101-1 and101-2 has memory cells MC arranged in a matrix manner.

[0417] The bit line controller 103C includes “m” data circuits 106. Thedata circuit 106 is connected one bit line BLa and reference bit lineBLb.

[0418] Since the structure of one cell MC of the NAND type EEPROM is thesame as that according to the first embodiment shown in FIGS. 3A and 3B,it is not described in detail. The cell MC comprises a plurality ofmemory cell transistors M1 to M4 connected to each other in series toform a NAND cell MC. An end of the cell MC is connected to a source lineVS through a selection transistor S2. A group of the memory celltransistors M sharing the control gate CG forms a unit called a page.Writing and reading of data is performed simultaneously to and from thepage. The group of the memory cell transistors M connected to fourcontrol gates CG1 to CG4 forms a unit called a block. The page and theblock respectively are selected by the control gate/selection gatedriver.

[0419] One memory cell transistor M has a floating gate (a chargestorage layer) and a control gate CG each of which is formed into alaminate shape to store data in accordance with the quantity ofelectrons stored in the floating gate. The quantity of stored electronscan be read as the threshold voltage of the memory cell transistor.

[0420] Data erase is performed from all of memory cell transistors M, inseries, connected between the selection transistors Si and S2. When datais erased from the memory cell transistor M, the control gate CG of thememory cell transistor M is grounded to apply positive and highpotential to a p-type well or a p-type substrate. As a result, electronsstored in the floating gate is discharged to the p-type well or thep-type substrate.

[0421] Writing of data is performed on all of memory transistorsconnected to one control gate CG. When data is written in the memorycell transistor M, electrons are injected into the floating gate by amethod contrary to the data erase operation. The quantity of electronsinjected into the floating gate can be read as the threshold voltage ofthe memory cell transistor M.

[0422]FIG. 21 is a graph showing distribution of threshold voltages ofthe memory cell transistor when multilevel data is stored. The axis ofabscissa stands for the threshold voltages, while the axis of ordinatestands for the number of memory cells.

[0423]FIG. 21 shows a case where four-levels formed of data “1”, “2”,“3” and “4” are stored in one memory cell transistor.

[0424] When data has been erased as shown in FIG. 21, the thresholdvoltage of the memory cell transistor M is made to be, for example, anegative-level. Data “1” corresponds to a case where the thresholdvoltage is a negative-level. Data “2” corresponds to a case where thethreshold voltage is 0.5V or higher and 0.8V or lower. Data “3”corresponds to a case where the threshold voltage is 1.5V or higher and1.8V or lower. Data “4” corresponds to a case where the thresholdvoltage is 2.5V or higher and 2.8V or lower.

[0425]FIG. 22 is a circuit diagram, in detail, showing the column-systemcircuit shown in FIG. 20. FIG. 20 shows an example of the structure inwhich the data circuit 106 is connected to one bit line BL. FIG. 22shows an example of a structure in which the data circuit 106 isconnected to four bit lines BL1 to BL4.

[0426] As shown in FIG. 22, the data circuit 106 includes two flip-flopcircuits 114-1 and 114-2. The flip-flop circuits 114-1 and 114-2 areconnected to four bit lines respectively provided for the right and leftportions. When the apparatus is turned on, one right bit line and oneleft bit line are selected from four bit lines. The selected bit linesare connected to the flip-flop circuits 114-1 and 114-2. Both of theflip-flop circuits 114-1 and 114-2 serve as sense amplifiers foramplifying and latching read data when the data reading operation isperformed. When data is written, the flip-flop circuits 114-1 and 114-2serve as data latches for latching write data. That is, each of theflip-flop circuits 114-1 and 114-2 is a sense amplifier/data latch.Moreover, the flip-flop circuits 114-1 and 114-2 are connected to awriting/verifying circuit 116 serving as a data writing circuit and averifying circuit.

[0427] When the writing/verifying circuit 116 writes data, it outputsany one of write control voltages VA1, VA2, VB1 and VB2 in accordancewith the combination of latch data latched by the flip-flop circuits114-1 and 114-2. The write control voltages VA1, VA2, VB1 and VB2 aregenerated by a write control voltage generating circuit (not shown).When data is read or when data is read for verification, thewriting/verifying circuit 116 controls the voltage of the bit line inaccordance with the combination-of data latched by the flip-flopcircuits 114-1 and 114-2.

[0428] The operation of the data circuit 106 shown in FIG. 22 will nowbe described.

[0429]FIGS. 23, 24 and 25 are waveforms showing a usual readingoperation and a verifying operation. In the operation waveforms shown inFIGS. 23, 24 and 25, the usual reading operation is indicated by a solidline and only portions of the verifying operation different from theusual reading operation are indicated by a broken line. Referring to thedrawings, T1 to T38 represent operation timings in a direction in whichtime passes in this order.

[0430]FIGS. 26, 27 and 28 are operation waveforms showing writingoperation, in which t1 to t4 operation timings.

[0431] Initially, a usual reading operation will now be described.

[0432] As shown in FIGS. 23, 24 and 25, a selected bit line BLa and areference bit line BLb are electrically charged to 1.2V and 1.0V,respectively. Then, the lines BLa and BLb are brought to a floatingstate. The potentials of the selection gates SG1 a and SG2 a on theselected row and a non-selected control gate CG are made to be 4V. Thepotentials of the selected control gates CG are 0V, 1V and 2V in thissequential order.

[0433] If the memory cell transistor M has stored data “1”, the memorycell transistor M is electrically conducted when the potential of theselected control gate CG is 0V. Therefore, the bit line is electricallydischarged (that is, an electric current flows toward the source lineVS) so that the voltage of the bit line is made to be 0V. If the memorycell transistor M has stored another data item at this time, no electriccurrent flows in the bit line so that the voltage 1.2V of the bit lineBLa is maintained.

[0434] Then, the voltage of the selected bit line BLa and the voltage(1.0V) of the reference bit line BLb are simultaneously applied to thetwo flip-flop circuits 114-1 and 114-2. If data is “1”, then both of anode D1A of the flip-flop circuit 114-1 and a node D2A of the flip-flopcircuit 14-2 are made to be “L”. If data is another data item, both ofthe nodes D1A and D2A are made to be “H”.

[0435] Then, the potential of the selected control gate CG is raisedfrom 0V to 1V, and whether or not an electric current flows in the bitline BLa is detected. In a case where the memory cell transistor M hasstored data “1” or “2” when the potential of the selected control gateCG has been raised to 1V, the potential of the bit line BLa is made tobe 0V. When the memory cell transistor M has stored data “3” or “4”, thepotential of the bit line BLa is maintained at 1.2V.

[0436] The voltage of the selected bit line BLa and the voltage of thereference bit line BLb are connected to the flip-flop circuit 114-1.When data is “1”, the levels of the nodes D1A and D2A are maintained at“L”. When data is “2”, the levels of the nodes D1A and D2A are “L, H”.When data is another data item, the levels of both of the nodes D1A andD2A are made to be “H” level.

[0437] Then, the potential of the selected control gate CG is raisedfrom 1V to 2V to detect whether or not an electric current flows in thebit line BLa. When the potential of the selected control gate CG hasbeen raised to 2V and the memory cell transistor M has stored data “1”,“2” or “3”, the voltage of the bit line BLa is made to be 0V. When thememory cell transistor M has stored data “4”, the voltage of the bitline BLa is maintained at 1.2V.

[0438] When the memory cell transistor M has stored data “2”, that is,when the levels of the nodes D1A and D2A are “L, H”, voltage VB2 is madeto be “H” level so that the voltage of the bit line is modified to be“H” level.

[0439] Then, the voltage of the selected bit line BLa and the voltage ofthe reference bit line BLb are connected to the second flip-flop circuit14-2. When data is “1”, both of the nodes D1A and D2A are made to be “L”level. When data is “2”, the nodes D1A and D2A are made to be “L, H”levels. Although the node D2A is made to be “L” level when data is “2”,the level “L” of the node D1A is used to modify the potential of the bitline BLa to “H” level. When data is “3”, the nodes D1A and D2Arespectively made to be “H, L”. When data is “4”, both of the nodes D1Aand D2A are made to be “H” level.

[0440] As described above, the four threshold voltages read from thememory cell transistor M are made to correspond to the four types oflatched data items in the flip-flop circuits 114-1 and 114-2.

[0441]FIG. 29 is a table showing the relationship between the thresholdvoltages of the memory cell transistor and latched data items (readdata).

[0442] Referring to FIGS. 26, 27 and 28, the writing operation will nowbe described.

[0443] The selected bit line BLa is, from the data circuit 106, appliedwith any one of voltage VA1=VM8 (about 8V), voltage VA2=2V, voltageVB1=1V or voltage VB2=0V. The selection of the voltages VA1, VA2, VB1and VB2 is performed in accordance with write data, that is, four typesof latched data items latched by the two flip-flop circuits 114-1 and114-2.

[0444]FIG. 30 is a table showing the relationship between latched dataitems (write data items) and the threshold voltages of the memory celltransistor.

[0445] The voltages VA1, VA2, VB1 and VB2 correspond to writing of data“1” to “4” . Potential VM8 of the voltage VA1 is set in such a mannerthat no electron is injected into the floating gate when the differencebetween potential VPP of the control gate CG and the potential of thesubstrate (the channel) is (VPP−VM8).

[0446] To write data in the memory cell transistor M belonging to theselected row, the potential of the selected control gate CG is set to behigh voltage VPP (about 20V), the potential of the non-selected controlgates is set to be voltage VM10CG (about 10V) to transfer the potentialVM8, the potential of the selection gate SG1 is set to be 0V to preventflow of a direct current from the bit line, and the potential of theselection gate SG2 is set to be voltage VM10SG (about 10V) to transferthe potential VM8.

[0447] The non-selected bit lines are applied with the potential VM8 toprevent change of the threshold voltage of the memory cell transistor Mbelong to the non-selected column. The application is performed bymaking the voltage VBLA to be the potential VM8 and by setting transfergate circuit drive signal BLC2D to BLC4D and signal DTCBB to be voltageVM10BL (about 10V) to transfer the potential VM8. Similarly, to transfervoltage VA1=VM8 voltage VBITH of the n-type well on which the p-channeltransistor for forming the flip-flop circuit, the signal BLC1, signalVRFY101-1 and signal VRFYA are set to be VM10BL.

[0448] If self-boost write method (K.D. Suh et al., 1995 ISSCC Digest ofTechnical Papers, pp. 128-129) is employed, the potential VM8, voltageVM10SG and voltage VM10BL may respectively be about 3V, 3V and 5V.

[0449] That is, in this specification, the potential of the channel of acell in which data is not required to be written is self-raised toprevent change in the threshold voltage of the memory cell transistorcaused from injection of electrons into the floating gate in a casewhere the writing operation is performed such that the bit line writecontrol is made to be Vcc (for example, 3V or 5V).

[0450] The self-boost writing method will now be described.

[0451] Initially, 0V is applied to the selected bit line BL1, while 3Vis applied to the non-selected bit line BL2. Then, the level of theselection gate SG1 of a drain side selection transistor is raised from0V to 3V to turn the transistor on so that the memory cell array isconnected to the bit lines BL1 and BL2. On the other hand, 0V is appliedto the source side selection gate SG2 so as to turn the selectiontransistor off so that the connection between the memory cell array andthe common source line CSL is disconnected. As a result, the channelpotential Vch of the cell array between two selection transistors SG1and SG2 is 0V commonly for the selected cell arrays connected to the bitline BL1. On the other hand, 3V is supplied to the non-selected cellarray from the bit line BL2.

[0452] Writing of data to the selected cell array will now be described.Only the control gate electrode of the selected cell is applied withhigh voltage (Vpp: for example, 18V) for writing. The state of theselected cell is such that the control gate electrode is 18V and thechannel potential is 0V. If the coupling ratio of the cell is 0.6, thedifference in the potential between the floating gate electrode and thesemiconductor substrate is 11V so that electrons are injected into thefloating gate electrode through a tunnel oxide film-thus, the thresholdvoltage of the cell is made to be positive so that data is written inthe selected cell. An intermediate potential (VM: for example, 10V) isapplied to the control gate electrode of each non-selected cells of theselected cell array. Since the coupling ratio is 0.6 as described above,the difference in the potential between the floating gate electrode andthe semiconductor substrate is 6V. With the foregoing potential, writingattributable to injection of the tunnel current is not performed withina usual writing time. Therefore, data is not written in the cells exceptfor the selected cells.

[0453] On the other hand, writing of data on the NAND cell arrayconnected to the non-selected bit line BL2 is inhibited as follows. Asdescribed above, 3V (power supply voltage Vcc) is applied to thenon-selected bit line BL2. When SG1 has been raised from 0V to Vcc, thatis, 3V, the selection transistor is turned on so that the potential of3V is applied from the bit line to the cell array connected to the bitline/BL2. All of the channel potentials (Vch) of the NAND cell array aremade such that Vch=Vcc−Vths assuming that the threshold voltage of theselection gate SG1. Then, the selection gate SG1 is turned off. That is,if Vcc=3V and Vths=1V, the channel potential of all of the cells of thenon-selected cell array is made such that Vch=3V−1V=2V. Thus, thechannel potential is electrically charged to 2V. On the other hand,since the selection gate SG2 has been turned off (the potential of SG2is 0), the channel potential Vch, (the potential in the source and drainregion and the diffusion layer between cells) of the non-selected NANDcell array is in a floating state. After the channel potential has beenbrought to the floating state, the voltage of the control gate is raisedto the writing voltage (Vpp=18V) or the intermediate potential (VM=10V).Since the channel potential is in the floating state at this time, thechannel potential is raised from 2V, which is the initial-level, to 8Vattributable to the voltage applied to the control gate. The degree ofthe self-boost is not determined in accordance with Vpp=18V but the sameis determined in accordance with VM=10V. The reason for this will now bedescribed. If a NAND cell array is formed by connecting, for example,four memory cells in series, only one control gate is applied withVpp=18V and VM=10V is applied to all of the three other control gates.Therefore, the influence of VM=10V is overwhelmingly great.

[0454] As a result of the above self-boosting, only a low voltage of 3Vis applied to the tunnel oxide film between the substrate and thefloating gate electrode of the non-selected NAND cell array even if thewriting voltage Vpp is 18V and the potential of the floating gateelectrode is about 11V (18V×0.6). As a result, no tunnel current flowsand writing of data on the non-selected NAND cell array is prevented.

[0455] Data is not written in the other cells of the non-selected NANDcell array because the difference in the potential to be applied to thetunnel oxide film is 2V because the voltage of the control gateelectrode is such that VM=10V, the voltage of the floating gateelectrode is 6V (10V×0.6) and the channel potential is about 8V.

[0456] Referring to FIGS. 23, 24 and 25, the verify reading operationwill now be described.

[0457] Similarly to the reading operation, the selected bit line BLa andreference bit line BLb respectively are electrically charged to 1.2V and1.0V, and then brought to the floating state. The potential of the twoselection gates SG1 and SG2 of the selected row and the potential of thenon-selected control gate CG are made to be 4V. The potentials of theselected control gates CG are sequentially made to be 0.5V, 1.5V and2.5V. The foregoing potentials respectively correspond to verificationof data “2”, that of data “3” and that of “4”.

[0458] Based on a result of the relationship between write data itemsand the threshold voltages of the memory cell transistor shown in FIG.30, latch data in the second flip-flop circuit 114-2 may be inverted tobe changed to write data of “1” if data “2” has been sufficientlywritten. If data “2” has been written insufficiently, latch data in theflip-flop circuit 114-2 may be maintained.

[0459] If data “3” has been sufficiently written, latch data in thefirst flip-flop circuit 114-1 is inverted to be changed to write data of“1”. If data “3” has not been sufficiently written, latch data in theflip-flop circuit 114-1 is maintained.

[0460] If data “4” has been sufficiently written, latched data items inthe first and second flip-flop circuits 114-1 and 114-2 respectively areinverted so as to be changed to write data of “1”. If data “4” has beenwritten insufficiently, latched data items in the two flip-flop circuits114-1 and 114-2 are maintained.

[0461] Initially, the potential of the selected control gate CG is madeto be 0.5V to verify data “2”. If the state of the threshold voltage ofthe read memory cell transistor corresponds to data “1”, an electriccurrent flows in the bit line. Therefore, the voltage of the bit line ismade to be 0V. If states of the threshold voltages of the read memorycell transistor M respectively correspond the data “2”, “3” and “4”, noelectric current flows in the bit line so that the voltage of the bitline is maintained at 1.2V.

[0462] To maintain the latching state of the flip-flop circuit whichwrites data “1”, data “3” or data “4”, the voltages of the respectivebit lines are made to be “H”, “H” and “L”. Then, the voltage of theselected bit line BLa and that of the reference bit line BLb are appliedto the second flip-flop circuit 114-2. The latching state of theflip-flop circuit which has not latched data “2” is not changed. If data“2” has been sufficiently written, the latching state of the flip-flopcircuit which has latched data “2” is changed to the writing latchingstate of data “1”. If data “2” has not been sufficiently written, thelatching state is maintained.

[0463] Then, the potential of the selected control gate CG is made to be1.5V to verify data “3”. If the state of the threshold voltage of theread memory cell transistor M corresponds to data “1” or “2”, anelectric current flows in the bit line BLa. Therefore, the voltage ofthe bit line BLa is made to be 0V. If the state of the threshold voltageof the read memory cell transistor M corresponds to data “3” or “4”, noelectric current flows in the bit line BLa so that the voltage of thebit line BLa is maintained at 1.2V.

[0464] To maintain the latching state of the flip-flop circuit whichwrites data “1”, data “2” or data “4”, the voltages of the respectivebit lines are made to be “H”, “H” and “L”. Then, the voltage of theselected bit line BLa and that of the reference bit line BLb are appliedto the first flip-flop circuit 114-1. The latching state of theflip-flop circuit which has not latched data “3” is not changed. If data“3” has been sufficiently written, the latching state of the flip-flopcircuit which has latched writing of data “3” is changed to the writinglatching state of data “1”. If data “3” has not been sufficientlywritten, the latching state is maintained.

[0465] Finally, the potential of the selected control gate CG is made tobe 2.5V to verify data “4”. If the state of the threshold voltage of theread memory cell transistor M corresponds to data “1”, “2” or “3”, anelectric current flows in the bit line BLa. Therefore, the voltage ofthe bit line BLa is made to be 0V. If the state of the threshold voltageof the read memory cell transistor M corresponds to data “4”, noelectric current flows in the bit line BLa so that the voltage of thebit line BLa is maintained at 1.2V.

[0466] To maintain the latching state of the second flip-flop-circuit114-2 which writes data “1”, data “2” or data “3”, the voltages of therespective bit lines are made to be “H”, “L” and “H”. Then, the voltageof the selected bit line BLa and that of the reference bit line BLb areapplied to the second flip-flop circuit 114-2. The latching state of theflip-flop circuit which has not latched data “4” is not changed. If data“4” has been sufficiently written, the latching state of the flip-flopcircuit which has latched writing of data “4” is changed to the writinglatching state of data “3”. If data “4” has not been sufficientlywritten, the latching state is maintained.

[0467] To maintain the state of the flip-flop circuit 114-1 which writesdata “1”, “2” or “3”, the voltages of the respective bit lines are madeto be “H”, “H” and “L”. Then, the voltage of the selected bit line BLaand that of the reference bit line BLb are connected to the flip-flopcircuit 114-1. The latching state of a flip-flop circuit which has notlatched writing of data “4” is not changed. The latching state of aflip-flop circuit which has latched writing of data “4” is changed tolatching state of writing of data “1” if data “4” has been sufficientlywritten. If data “4” has not been sufficiently written, the latchingstate is maintained.

[0468] After the foregoing operation has been performed, writecompletion detection signal PENDA brought to be the floating state afterthe electric charge is charged maintains “H” level when the latchingstate of all of the flip-flop circuits 114-1 and 114-2 has been broughtto the latching state of data “1”. Thus, the writing operation can becompleted.

[0469] On the other hand, if at least either the flip-flop circuit 114-1or 114-2 is in the latching state of data “2” to “4”, the writecompletion detection signal PENDA is brought to “L” level. Thus, theoperation is again shifted to the writing operation.

[0470] As described above, according to the fourth embodiment,four-level voltages to be applied to the bit line are switched by thedata circuit 106 comprising the flip-flop circuit 114-1 and 114-2 whichare sense amplifiers and data latches and the writing/verifying circuit116 serving as the data writing circuit and the verifying circuit toselectively apply the voltage to the bit line as DC bias. The number ofthe column-system circuits, and more particularly, the number of thecircuits serving as the sense amplifiers and data latches and thewriting and verifying circuits can be reduced. Therefore, a nonvolatilesemiconductor memory device can be provided.

[0471] (Fifth Embodiment)

[0472]FIG. 31 is a diagram showing the structure of a multilevel storingNAND type EEPROM according to a fifth embodiment of the presentinvention.

[0473] The multilevel storing NAND type EEPROM according to the fifthembodiment has a single end structure different from the open bitstructure according to the fourth embodiment.

[0474] As shown in FIG. 31, the multilevel storing NAND type EEPROMaccording to the fifth embodiment has a row-system circuit 102 and acolumn-system circuit 103 provided for a memory cell array 101 havingmemory cells arranged in the matrix manner.

[0475] The row-system circuit 102 includes a row decoder 102A forreceiving an address signal output from an address buffer 104 andselecting a row of the memory cell array 101 in response to the suppliedaddress signal, and a word line driver 102B for driving a word line ofthe memory cell array 101 in accordance with an output from the rowdecoder 102A. In the case of the NAND type EEPROM, the word lines areselection gates and control gates. The word line driver is also called acontrol gate/selection gate driver.

[0476] The column-system circuit 103 includes a column decoder 103A forreceiving the address signal output from the address buffer 104 andselecting a column in the memory cell array in response to the suppliedaddress signal and a column selection line driver 103B for driving acolumn selection line for selecting a column in the memory cell array inaccordance with an output from the column decoder 103A.

[0477] The column-system circuit 103 is provided with a bit linecontroller 103C for temporarily storing data to be written in the memorycell and reading data in the memory cell.

[0478] The bit line controller 103C is, through a data input/output lineI/O, connected to a data input/output circuit (data input/output buffer)105. The bit line controller 103C is, through a bit line BL, connectedto the memory cell of the memory cell array 101.

[0479] When data is written, the bit line controller 103C receives writedata from the data input/output buffer 105 to output supplied write datato the memory cell. When data is read, the bit line controller 103Creceived read data from the memory cell to output supplied read data tothe data input/output buffer 105.

[0480] The data input/output buffer 105 performs control input andoutput of data such that it introduces write data supplied from theoutside of the EEPROM to a memory core portion and outputs data readfrom the memory core portion to the outside of the EEPROM.

[0481] The write completion detecting circuit 118 detects whether or notwriting data has been completed in accordance with an output from thebit line controller.

[0482]FIG. 32 is a diagram showing the structures of the memory cellarray and the column-system circuit shown in FIG. 31.

[0483] As shown in FIG. 32, the memory cell array 101 has memory cellsMC arranged in a matrix manner.

[0484] The bit line controller 103C includes “m” data circuits 106A. Thebit line controller 106A is connected to one bit line BL.

[0485] As shown in FIG. 32, the cell MC has a similar circuit structureto that according to the fourth embodiment, that is, the firstembodiment. Moreover, the following facts are similar to those of thefourth and first embodiments, that the group of the memory celltransistors M sharing the control gate CG forms a unit called a page,writing and reading of data are performed simultaneously to and from inthe unit of page, the group of memory cell transistors M connected tothe four control gates CG1 to CG4 forms a unit called a block, and thepage and the block are selected by the control gate/selection gatedriver. The structure of the memory cell transistor M is similar to thatshown in FIG. 3A. The level of the threshold voltage when four-leveldata is stored in one memory cell transistor M may be set similarly tothe method shown in FIG. 21.

[0486]FIG. 33 is a circuit diagram showing the bit line controller 106Ashown in FIG. 32.

[0487] Although FIG. 32 shows an example of the structure in which thebit line controller 106A is connected to one bit line, FIG. 33 shows anexample of the structure in which the bit line controller 106A isconnected to four bit lines. The foregoing structure shown in FIG. 33will now be described.

[0488] As shown in FIG. 33, the bit line controller 106A includes twoflip-flop circuits 114A-1 and 114A-2. The flip-flop circuits 114A-1 and114A-2 are connected to four bit lines. When the operation is performed,one bit line is selected from four bit line. The selected bit line isconnected to the flip-flop circuits 114A-1 and 114A-2. Both of theflip-flop circuits 114A-1 and 114A-2 serve as sense amplifiers foramplifying and latching read data when data is read, while same serve asdata latch for latching write data when data is written. That is, theflip-flop circuits 114A-1 and 114A-2 are sense amplifiers/data latches.

[0489] The flip-flop circuits 114A-1 and 114A-2 are different from-thoseaccording to the fourth embodiment in that each of the flip-flopcircuits 114A-1 and 114A-2 has a forcible reverse sense amplifier. Theforcible reverse sense amplifier is described in, for example, thefollowing document: K. D. Suh et al., 1995 ISSCC Digest of TechnicalPapers, pp. 128-129.

[0490] Moreover, the flip-flop circuits 114A-1 and 114A-2 are connectedto a writing/verifying circuit 116A.

[0491] The writing/verifying circuit 116A outputs, to the bit line, anyone of write control voltages V1, V2, V1 and V2 in accordance with thecombination of latched data items latched by-the flip-flop circuits114A-1 and 114A-2. When data is read or data is read for verification,the writing/verifying circuit 116A controls the voltage of the bit linein accordance with the combination of latched data items latched by theflip-flop circuits 114A-1 and 114A-2.

[0492] The operation of the bit line controller shown in FIG. 33 willnow be described.

[0493]FIG. 34 is a waveform showing a usual reading operation and averifying operation. In the operation waveform shown in FIG. 34, theusual reading operation is indicated by a solid line and only portionsof the verifying operation different from the usual reading operationare indicated by a broken line.

[0494]FIG. 35 is an operation waveform showing the writing operation.

[0495] First, the usual reading operation will now be described.

[0496] The selected bit line BL is precharged, as shown in FIG. 34, andthen brought to a floating state. Simultaneously, the node D1A of theflip-flop circuit 114A-1 and the node D2A of the flip-flop circuit114A-2 are reset to “L”. The potential of the two selected selectiongates SG1 and SG2 and the potential of the non-selected control gate CGare set to be 4V. The potentials of the selected control gate CG aresequentially made to be 2V, 1V and 0V.

[0497] In a case where the selected memory cell transistor M has storeddata “4”, the memory cell transistor M is not electrically conductedwhen the potential of the control gate CG is 2V. As a result, noelectric current flows in the bit line so that the voltage of the bitline is maintained at “H”. In a case where the selected memory celltransistor M has stored data “1”, “2” or “3”, the memory cell transistorM is electrically conducted when the potential of the selected controlgate CG is 2V. Thus, an electric current flows in the bit line so thatthe voltage of the bit line is made to be 0V. Then, the voltage of theselected bit line is applied to the two flip-flop circuits 114A-1 and114A-2. When data is “4”, both of the nodes D1A and D2A are made to be“H”. When data is another data item, both of the nodes D1A and D2A aremade to be “L”.

[0498] Then, the bit line BL is again precharged, and the potential ofthe selected control gate is made to be 1V. When the selected memorycell transistor M has stored data “1” or “2”, the potential of the bitline is made to be 0V. When the selected memory cell transistor M hasstored data “3” or “4”, the potential of the bit line is maintained at“H”. Then, the voltage of the selected bit line is applied to theflip-flop circuit 114A-1. When data is “4”, the nodes D1A and D2A aremaintained at “H”. When data is “3”, the nodes D1A and D2A are made tobe “H, L”. When data is “2” or “1”, both of the nodes D1A and D2A aremaintained at “L”.

[0499] Then, the bit line BL is again precharged. Moreover, the selectedcontrol gate is made to be 0V. When data is “2”, “3” or “4”, the bitline is maintained at “H”. When data is “1”, the bit line is made to be“L”. When data stored by the memory cell transistor M is “3”, that is,when the nodes D1A and D2A respectively are “H, L”, voltage V2=0V istransferred to modify the voltage of the bit line to “L”. Then, thevoltage of the selected bit line is supplied to the flip-flop circuit114A-2. When data is “4”, body of the nodes D1A and D2A are maintainedat “H”. When data is “3”, the nodes D1A and D2A respectively maintainedat “H, L”. When data is “2”, the nodes D1A and D2A respectively aremaintained-at “L, H”. When data is “1”, both of the nodes D1A and D2Aare maintained at “L”.

[0500] As described above, the levels of the four types of thresholdvoltages read from the memory cell transistor M can be made tocorrespond to four types of latched, data items in the flip-flopcircuits 114A-1 and 114A-2, similarly to the fourth embodiment shown inFIG. 29.

[0501] Since the writing operation is, as shown in FIG. 35, performedsimilarly to that according to the fourth embodiment described withreference to FIGS. 26 to 28, the writing operation is omitted fromdescription.

[0502] Then, the verifying operation will now be described.

[0503] The selected bit line BL is electrically charged similarly to thereading operation, and then brought to a floating state. The potentialof the two selected selection gates SG1 and SG2 and that of thenon-selected control gate CG are made to be 4V. The potentials of theselected control gate CG are sequentially made to be 2.5V, 1.5V and0.5V. The foregoing potentials correspond to verification of data “4”,that of data “3” and that of data “2”.

[0504] Initially, the potential of the selected control gate CG is madeto be 2.5V to verify data “4”. If the state of the threshold voltage ofthe read memory cell transistor M corresponds to data “4”, no electriccurrent flows in the bit line. Therefore, the voltage of the bit line ismaintained in the precharge state. If the state of the threshold voltageof the read memory cell transistor M is data “1”, “2” or “3”, anelectric current flows in the bit line. Therefore, the voltage of teebit line is made to be 0V.

[0505] To maintain the latching state of the flip-flop circuit whichwrites data “1”, “2” or “3”, the voltage of the bit line is made to be“L”. Then, the voltage of the selected bit line is applied to theflip-flop circuits 114A-1 and 114A-2. At this time, the latching stateof the flip-flop circuit which has not latched writing of data “4” isnot changed. The-latching state of the flip-flop circuit which haslatched writing of data “4” is changed to the latching state of writingof data “1” if data “4” has been sufficiently written. If data “4” hasnot been sufficiently written, the latching state is maintained.

[0506] Then, the potential of the selected control gate CG is made to be1.5V to verify data “3”. If the state of the threshold voltage of theread memory cell transistor M corresponds to data “1” or “2”, anelectric current flows in the bit line. Therefore, the voltage of thebit line is made to be 0V. If the state of the threshold voltage of theread memory cell transistor M corresponds to data “3” or “4”, noelectric current flows in the bit line. Thus, the voltage of the bit,line is maintained at the precharge level.

[0507] To maintain the latching state of the flip-flop circuit whichwrites data “1”, “2” or “4”, the voltages of the respective bit linesare made to be “L”. Then, the voltage of the selected bit line isapplied to the flip-flop circuit 114A-1. At this time, the latchingstate of the flip-flop circuit which has not latched writing of data “3”is not changed. If data “3” has been sufficiently written, the latchingstate is changed to the latching state of writing of data “1”. If data“3” has been sufficiently written, the latching state is maintained.

[0508] Finally, the potential of the selected control gate CG is made tobe 0.5V to verify data “2”. If the state of the threshold voltage of theread memory cell transistor M corresponds to data “2”, “3” or “4”, noelectric current flows in the bit line. Therefore, the voltage of thebit line is maintained to the precharge level. If the state of the ofthe read memory cell transistor M corresponds to data “1”, no electriccurrent flows in the bit line. Therefore, the voltage of the bit line ismade to be 0V.

[0509] To maintain the latching state of the flip-flop circuit 114A-2which has latched writing of data “1”, “3” or “4”, the voltages of therespective bit lines are made to be “L”. Then, the voltage of theselected bit line is connected to the flip-flop circuit 114A-2. Thelatching state of the flip-flop circuit which has not latched writing ofdata “2” is not changed. The latching state of the flip-flop circuitwhich has latched writing of data “2” is changed to a latching state ofwriting of data “1” if data “2” has been sufficiently written. If data“2” has been sufficiently written, the latching state is maintained.

[0510] After the above-mentioned operation has been completed and all ofthe latching states of the flip-flop circuits 114A-1 and 114A-2 havebeen brought to the latching state for writing data “1”, the “H” levelof the write completion detection signal PEND is maintained. Thus, thewriting operation can be ended.

[0511] If at least either the flip-flop circuit 114A-1 or the flip-flopcircuit 114A-2 is in the latching state for writing data “2” to “4”, thewrite completion detection signal PEND is brought to “L”. Then, theoperation is again shifted to the writing operation.

[0512] The four-level storing NAND type EEPROM according to the fourthand fifth embodiments has the structure such that the verifying circuitand the writing circuit are controlled by “n” write data items latchedby the flip-flop (a data latch/sense amplifier circuit). As a result,when the number of the multilevel is made such that 2^(m) (m is anatural number not smaller than 2)=n, the number of the data latch/senseamplifier circuits can be made to be “m”. Specifically, when four-leveldata is treated, use of only two flip-flop circuits serving as the datalatches/sense amplifiers enables a bit line controller to be formed.Therefore, the size of the column-system circuit, and more particularly,the number of the sense amplifier/data latch circuits and the verifyingcircuits can be decreased. Therefore, a nonvolatile semiconductor memorydevice suitable to form a highly integrated structure can be obtained.

[0513] When a result of the verify reading operation is valid, theflip-flop circuit sequentially updates latched write data whenever aresult “sufficient writing” is realized to make the four-level data suchthat write data is “1” to correspond to write data when data in thememory cell transistor M has not been changed, specifically, to thethreshold voltages of the four-levels. As a result, the verify circuitand the writing circuit are controlled similar to the case where data“1” has been written.

[0514] When the number of multilevel data items is made to be 2^(m), anapparatus having the structure comprising “m” flip-flop circuits, duringverify operation, sometimes encounters change of updated write data.However, the verify circuit and the writing circuit are structured tosupply-another data item to the flip-flop circuit to correspond to writedata latched by the flip-flop circuit to prevent change of updated writedata.

[0515] Whenever the result “sufficient writing” is realized, n-leveldata items which are latched by the flip-flop circuit are sequentiallyupdated to write data “1”. Moreover, change of updated write data can beprevented. As a result, completion of writing can automatically bedetected because all of n-level data items which are latched by theflip-flop circuit are updated to write data “1”.

[0516] Also during the reading operation, read data detected by theflip-flop circuit is sometimes changed. The foregoing embodiment has thestructure such that a portion of latched read data is used to supplydata for preventing change of detected read data to the flip-flopcircuit. Also the foregoing structure is able to make the number of theflip-flop circuit to be “m” when the number of multilevel data items is2^(m).

[0517] (Sixth Embodiment)

[0518]FIG. 36 is a diagram showing the structure of a multilevel storingNAND type EEPROM according to a sixth embodiment of the presentinvention.

[0519] As shown in FIG. 36, the multilevel storing NAND type EEPROMaccording to the sixth embodiment has a structure called an open bitstructure. The open bit type multilevel storing NAND type EEPROM hasmemory cell arrays 201-1 and 201-2 having memory cells arranged in amatrix manner, row-system circuits 202-1 and 202-2 provided tocorrespond to the memory cell arrays 201-1 and 201-2 and a column-systemcircuit 203 arranged to be commonly used by the memory cell arrays 201-1and 201-2.

[0520] The row-system circuits 202-1 and 202-2 have a row decoder 202Afor receiving an address signal output from an address input circuit(address buffer) 204 to select a row in a memory cell array inaccordance with the supplied address signal, and a word line driver 202Bfor driving a word line of memory cell arrays in accordance with anoutput from the row decoder 202A. In the case of the NAND type EEPROM,the word lines are selection gates SG (SGA and SGB) and control gates CG(CGA and CGB). The word line driver is also called a controlgate/selection gate driver.

[0521] The column-system circuit 203 which is commonly used by thememory cell arrays 201-1 and 201-2 has a column decoder 203A forreceiving the address signal output from the address buffer 204 toselect a column in the memory cell array in response to the suppliedaddress signal, and a column selection line driver 203B for driving acolumn selection line for selecting a column of the memory cell array inaccordance with an output from the column decoder 203A.

[0522] Moreover, the column-system circuit 203 has a bit line controller203C including a data circuit for temporarily storing data to be writtenin the memory cell and reading data in the memory cell.

[0523] The bit line controller 203C is connected to a data input/outputcircuit (data input/output buffer) 205 through a data input/output lineI/O. Moreover, the bit line controller 203C is, through a bit line BLa,connected to a memory cell of the memory cell array 201-1 and a memorycell of the memory cell array 201-2.

[0524] The bit line controller 203C receives write data from the datainput/output buffer 205 when data is written to output received writedata to the memory cell array. The bit line controller 203C receivesread data from the memory cell when data is read to output the suppliedread data to the data input/output buffer 205.

[0525] The data input/output buffer 205 controls input and output ofdata such that it introduces write data supplied from outside of theEEPROM to a memory core portion and outputs data read from the memorycore portion to the outside of the EEPROM.

[0526] The write completion detecting circuit 218 detects whether or notwriting of data has been completed in accordance with an output from thebit line controller.

[0527]FIG. 37 is a diagram showing the structures of the memory cellarray and the column-system circuit shown in FIG. 36. FIG. 38A is adiagram showing a state of voltage input when data is read from thememory cell shown in FIG. 37. FIG. 38B is a diagram showing voltageinput waveforms and output waveforms appearing on the bit line.

[0528] As shown in FIG. 37, each of the memory cell arrays 201-1 and201-2 has memory cells MC arranged in a matrix manner.

[0529] The bit line controller 203C includes “m” data circuits 206. Thedata circuit 206 is connected one bit line BLa and reference bit lineBLb.

[0530] As shown in FIG. 38A, the NAND type EEPROM has a structure suchthat its one cell MC includes a plurality of memory cell transistors M1to M4 connected in series so that a NAND type cell MC is formed. An endof the cell MC is connected to the bit line BL through the selectiontransistor S1, while another end of the same is connected to the sourceline VS through the selection transistor S2. The group of the memorycell transistors M sharing the control gate CG forms a unit called a“page”. Writing and reading of data are simultaneously performed withrespect to the page. A group of the memory cell transistors M connectedto the four control gates CG1 to CG4 forms a unit called a “block”. Thepage and the block are selected by the control gate/selection gatedriver 202B.

[0531] The memory cell transistor M stores multilevel data in accordancewith the level of the threshold voltage. The apparatus according to thepresent invention reads the level of the threshold voltage as shown inFIGS. 38A and 38B. In this embodiment, memory cell transistor M2 havingthe control gate CG2 has been selected. Voltages as shown in FIG. 38Aare applied to the portions. The bit line BL is brought to a floatingstate. When the bit line BL is previously reset to 0V, the bit line BLis electrically charged by the common source line VS through the NANDcell. The selection gates and the control gate voltages are controlledin such a manner that the potential of the electrically charged bit lineBL is determined by the threshold voltage of the selected memory cellM2. In this embodiment, the selection gates SG1 and SG2, the controlgates CG1, CG3 and CG4 are made to be 6V, the selected control gate CG2is made to be 2V and the common source line VS is made to be 6V. Thevoltage waveforms are shown in FIG. 38B. If the potential of the bitline BL is 0V, the threshold voltage is 2V or higher. If the potentialof the bit line is 3.5V, the threshold voltage is −1.5V or lower. Inorder to simplify the description, the expression the “thresholdvoltage” is a level determined in consideration of a back bias.

[0532] After electrons have been discharged from the floating gate ofthe memory cell as a result of the erasing operation, electrons areinjected into the floating gate as a result of the writing operationwhich is performed in accordance with write data.

[0533]FIG. 39 is a graph showing output voltage which appears on the bitline and the number of the memory cells.

[0534] In a case where one memory cell has three states (data “0”, “1”or “2”), a state where the output voltage from the bit line is 3.5V to4.5V (a state where the threshold voltage is about −2.5V to −1.5V) asshown in FIG. 39 is made to be data “0” (erased), a state where theoutput voltage from the bit line is 1.5V to 2.5V (a state where thethreshold voltage is about −0.5V to 0.5V) is made to be data “1” and astate where the output voltage from the bit line is 0V to 0.5V (a statewhere the threshold voltage is about 1.5V to 2.5V) is made to be “2”.

[0535]FIG. 40 is a circuit diagram showing the detailed structure of adata circuit 206 shown in FIG. 37. The data circuit 206 shown in FIG. 40has a structure for storing three-levels.

[0536] As shown in FIG. 40, write/read data is latched by a flip-flopFF1 formed of n-channel MOS transistors Qn21, Qn22 and Qn23 andp-channel MOS transistors Qp9, Qp10 and Qp11 and a flip-flop FF2 formedof n-channel MOS transistors Qn29, Qn30 and Qn31 and p-channel MOStransistors Qp16, Qp17 and Qp18. The foregoing flip-flops FF1 and FF2serve as sense amplifiers.

[0537] The flip-flop FF1 latches whether “0” is written or other (i.e.,“1” or “2”) is written as write data information and senses and latcheswhether the memory cell has information of “0” or information of “1” or“2” as data information. The flip-flop FF2 latches whether “1” iswritten or “2” is written as data information and senses and latcheswhether the memory cell has information of “1” or information of “2” asread data information.

[0538] The data input/output lines I/OA and I/OB and the flip-flop FF1are connected to each other through the n-channel MOS transistors Qn28and Qn27. The data input/output lines I/OC and I/OD and the flip-flopFF2 are connected to each other through the n-channel MOS transistorsQn35 and Qn36. The data input/output lines I/OA, I/OB, I/OC and I/OD arealso connected to the data input/output buffer 205 shown in FIG. 36.

[0539] The gates of the n-channel MOS transistors Qn27, Qn28, Qn35 andQn36 are connected to the output of a column address decoder formed of aNAND logic circuit G2 and an inverter I4. The n-channel MOS transistorsQn26 and Qn34 equalizes flip-flops FF1 and FF2 when signals ECH1 andECH2 are “H”. The n-channel MOS transistors Qn24 and Qn32 control theconnection between the flip-flops FF1 and FF2 and a MOS capacitor Qd1.The n-channel MOS transistors Qn25 and Qn33 control the connectionbetween the flip-flops FF1 and FF2 and a MOS capacitor Qd2.

[0540] A circuit formed of the p-channel MOS transistors Qp12 and Qp13changes the gate voltage of the MOS transistor Qd1 in accordance withdata in the flip-flop FF1 and in response to activating signal VRFYBA. Acircuit formed of the p-channel MOS transistor Qp14 and Qp15 changes thegate voltage of the MOS capacitor Qd2 in accordance with data in theflip-flop FF1 and in response to activating signal VRFYBB. A circuitformed of the n-channel, MOS transistors Qn1 and Qn2 changes the gatevoltage of the MOS capacitor Qd1 in accordance with data in theflip-flop FF2 and in-response to activating signal RRFYBA1. A circuitformed of the n-channel MOS transistors Qn3 and Qn4 changes the gatevoltage of the MOS capacitor Qd2 in accordance with data in theflip-flop FF2 and in response to activating signal VRFYBB1.

[0541] Each of the MOS capacitors Qd1 and Qd2 comprises depletionn-channel MOS transistors and have capacities which are sufficientlysmaller than the capacity of the bit line. The n-channel MOS transistorQn37 electrically charges the MOS capacitor Qd1 in response to signalPREA. The n-channel MOS transistor Qn38 electrically charges the MOScapacitor Qd2 to voltage VB in response to signal PREB. The n-channelMOS transistors Qn39 and Qn4O control the connection between the datacircuit 206 and the bit lines B1a and B1b in response to signals BLCAand BLCB. A circuit formed of the n-channel MOS transistors Qn37 andQn38 also serves as a bit line voltage controller. A circuit formed ofthe p-channel MOS transistors Qp12 and QP13, a circuit formed of thep-channel MOS transistors Qp14 and Qp15, a circuit formed of then-channel MOS transistors Qn1 and Qn2 and a circuit formed of then-channel MOS transistors Qn3 and Qn4 also serve as bit line voltagecontrollers.

[0542] The operation of the EEPROM having the above-mentioned structurewill now be described with reference to the operation waveform. In thefollowing description, a state where control gate CG2A has been selectedwill now be described.

[0543] Reading Operation

[0544]FIG. 41 is an operation waveform showing a reading operation.

[0545] As shown in FIG. 6, at time t_(1R), the selected control gateCG2A in the block selected by the control gate/selection gate driver202B is made to be 2V, and non-selected control gates CG1A, CG3A andCG4A and selection gates SG1A and SG2A are made to be 6V. The sourcepotential of the memory cell is made to be 6V. If the memory cell is“0”, the bit line BLa is made to be 3.5V or higher. If it is “1”, thebit line BLa is made to be 1.5V or higher and 2.5V or lower. If it is“2”, the bit line BLa is made to be 0.5V or lower. The reference bitline BLb is electrically charged from VB to 3V. If voltage dropcorresponding to the threshold voltage of the n-channel MOS transistorQn40 raises a problem, the level of the signal BLCA is required to beraised.

[0546] At time t_(2R), the levels of the nodes N1 and N2 of thecapacitors Qd1 and Qd2 are made to be 1.5V, and then brought to afloating state. At time t_(3R), BLCA and BLCB are made to be Vcc (forexample, 5V) so that the potentials of the bit lines BLa and BLb aretransferred to N1 and N2. Then, the signals BLCA and BLCB are again madeto be “L” so that the bit line BLa and the MOS capacitor Qd1 areseparated from each other and the bit line BLb and the MOS capacitor Qd2are separated from each other. The signals SAN1 and SAP1 arerespectively brought to “L, H” so that the flip-flop FF1 is deactivated.Thus, the signal ECH1 is made to be “H” so that it is equalized. Then,signals RV1A and RV1B are made to be “H”. When voltage dropcorresponding to the threshold voltages of the n-channel MOS transistorsQn24 and Qn25 raises a problem, the levels of the signals RV1A and RV1Bare required to be raised. At time t_(4R), the signals SAN1 and SAP1respectively made to be “H, L”, the voltages of the nodes N1 and N2 aresensed and latched. As a result, a fact that data in the memory cell is“0” or other (i.e., “1” or “2”) is sensed by the flip-flop FF1 and itsinformation is latched by the same.

[0547] Then, whether the memory cell is “1” or “2” is sensed.

[0548] At time t_(5R), the dummy bit line BLb is electrically chargedfrom VB to 1V. At time t_(6R), the nodes N1 and N2 of the capacitors Qd1and Qd2 are made to be 1.5V, and then brought to a floating state. Thesignals BLCA and BLCB are again made to be “L” so that the bit line BLaand the MOS capacitor Qd1 are separated from each other and the bit lineBLb and the MOS capacitor Qd2 are separated from each other. The signalsSAN2 and SAP2 respectively are made to be “L” and “H” so that theflip-flop FF2 is deactivated. Moreover, the signal ECH2 is made to be“H”so as to be equalized. Then, the signals RV2A and RV2B are made to be“H”. At time t_(7R), the signals SAN2 and SAP2 respectively are againmade to be “H” and “L” so that the voltage of the node N1 is sensed andlatched. Thus, whether data in the memory cell is “1” or “2” is sensedby the flip-flop FF2 and information of this is latched by the same.

[0549]FIG. 42 is a table showing data which is sensed and latched by theflip-flops FF1 and FF2.

[0550] As shown in FIG. 42, data in the flip-flops FF1 and FF2 areoutput to the data input/output lines I/OA, I/OB, I/OC and I/OD.

[0551] Data to be output to the outside of the chip may be data obtainedby converting signals output to the data input/output line I/OA, I/OB,I/OC and I/OD by the data input/output buffer 205.

[0552] Writing Operation

[0553] Prior-to performing the writing operation, supplied data for twobits is converted by the data input/output buffer 205 so as to besupplied to the bit line controller 203C (the data circuit 206).

[0554]FIG. 43 is a table showing data to be supplied to the data circuit206 and latched by the flip-flops FF1 and FF2. The relationship betweenfour-level data and the data input/output line I/OA, I/OB, I/OC and I/ODis as shown-in FIG. 43.

[0555] Converted ternary data is transferred to a data circuit at acolumn address instructed with the address signal when the columnactivating signal CENB is “H”.

[0556]FIG. 44 is an operation waveform showing the writing operation.

[0557] At time t_(1w), voltage VA is made to be the bit line writingcontrol voltage 1V so that the bit line BLa is made to be 1V. Whenvoltage drop of the n-channel MOS transistor Qn39 corresponding to thethreshold voltage raises a problem, the level of the signal BLCA isrequired to be raised. Then, the signal PRE is made to be “L” so thatthe bit line is brought to a floating state. At time t_(2w), the signalRV2A is made to be 1.5V. As a result, bit line control voltage of 0V isapplied to the bit line of the columns having data “2”. When thethreshold voltage of the n-channel MOS transistor Qn32 is made to be 1V,the n-channel MOS transistor Qn32 is turned off when “0” or “1” iswritten. When “2” is written, the n-channel MOS transistor Qn32 isturned on. Then, VRFYBA is made to be 0V at time t_(3w), and bit linewrite control voltage Vcc (for example, 5V) is output from a datacircuit having data “0” to the bit line.

[0558] As a result, bit lines for writing “0” are made to be Vcc, bitlines for writing “1” are made to be 1V and bit lines for writing “2”are made to be 0V.

[0559] At time t_(1w), selection gate SG1A and control gates CG1A toCG4A of the block selected by the control gate/selection gate driver202B are made to be Vcc. The selection gate SG2A is made to be 0V. Then,the selected control gate CG2A is made to be high voltage of VPP (forexample, 20V), while the non-selected control gates CG1A, CG3A and CG4Aare made to be intermediate voltage of VM (for example, 10V). In thememory cell corresponding to a data circuit storing data “2”, thedifference in the potential between the channel potential of 0V and VPPof the control gate caused electrons to be injected into the floatinggate so that the threshold voltage is increased. In the memory cellcorresponding to the data circuit storing data “1”, the difference inthe potential between the channel potential of 1V and VPP of the controlgate causes electrons to be injected into the floating gate so that thethreshold voltage is increased. The reason why the channel potential ismade to be 1V is that the quantity of electrons may be smaller ascompared with the case in which data “2” is written. In the memory cellcorresponding to the data circuit storing data “0”, the difference inthe potential between the channel potential and VPP of the control gateis small. Therefore, substantially no electrons is injected into thefloating gate. Therefore, the threshold voltage of the memory cell isnot changed. During the writing operation, signals SAN1, SAN2, VRFYBB,PREB and BLCB are “H” level, signals SAP1, SAP2, RV1A, RV1B, RV2B, ECH1and ECH2 are “L” level and the voltage VB is 0V.

[0560] Verify Reading Operation

[0561]FIG. 45 is an operation waveform showing the verify readingoperation.

[0562] At time t_(1RV), the selected control gate CG2A in the blockselected by the control gate/selection gate driver 202B is made to be2V, the non-selected control gates CG1A, CG3A and CG4A and the selectiongates SG1A and SG2A are made to be 6V. The potential of the memory cellis made to be 6V. When data “0” is written, the bit line BLa is made tobe 3.5V or higher. When data “1” has been sufficiently written, the bitline BLa is made to be 2.5V or lower. When data “1” has been writteninsufficiently, it is made to be 1.5V or higher. When data “2” has beensufficiently written, it is made to be 0.5V or lower. When data “2” hasbeen written insufficiently, it is made to be 0.5V or higher. The dummybit line BLb is electrically charged from VB to 2.5V. The reason why thepotential of the dummy bit line BLb is made to be a level lower, by0.5V, than 3V employed when data “1” is read is that data must besufficiently written in the memory cell. When degree of voltage dropcorresponding to the threshold voltage of the n-channel MOS transistorQn40 raises a problem, the level of the signal BLCA must be raised.

[0563] At time t_(2RV), the nodes N1 and N2 of the capacitors Qd1 andQd2 are made to be 1.5V, and then brought to a floating state. At timet_(3RV), VRFYBB1 is made to be “H”. As can be understood from FIG. 42,the node N6 is made to be “H” only when data “2” is written. Therefore,the dummy bit line BLb for writing data “2” is made from Vref to 0.5V.The reason why the potential of the dummy bit line BLb for writing data“2” is that data must be sufficiently written. When data “0” or “1” iswritten, the n-channel MOS transistor Qn4 is turned off because the nodeN6 is “L” and thus the dummy bit line BLb holds 2.5V.

[0564] At time t_(4RV), the control gate BLCA and BLCB of the transfergates 207-1 and 207-2 are made to be Vcc (for example, 5V) so that thepotentials of the bit lines BLa and BLb are transferred to the nodes N1and N2. Then, the signals BLCA and BLCB are again made to be “L” so thatthe bit line BLa and the MOS capacitor Qd1 are separated from each otherand the bit line BLb and the MOS capacitor Qd2 are separated from eachother.

[0565] At time t_(5RV), the signal RV1A is made to be 1.5V. As a result,node N1 of the column for writing data “0” is grounded. When thethreshold voltage of the n-channel MOS transistor Qn24 is made to be 1V,the n-channel MOS transistor Qn24 is turned off when “1” or “2” iswritten. When “0” is written, the n-channel MOS transistor Qn24 isturned on.

[0566] The signals SAN1 and SAP1 are made to be “L” and “H” so that theflip-flop FF1 is deactivated. When the signal ECH1 is made to be “H” soas to be equalized. Then, the signals RV1A and RV1B are made to be “H”.When the degree of voltage drop corresponding to the threshold voltageof the n-channel MOS transistors Qn24 and Qn25 raises a problem, thelevels of the signals RV1A and RV1B are required to be raised. At timet_(4R), the signals SAN1 and SAP1 are again made to be “H” and “L” sothat the voltages of the nodes N1 and N2 are sensed and latched.

[0567] As described above, in the data circuit storing write data of“1”, whether or not data in the corresponding memory cell has beensufficiently brought to the state for writing “1” is detected. If datain the memory cell is “1”, the flip-flop FF1 senses and latches thevoltage of the node N1 so that the write data is changed to “1”. If datain the memory cell is not “1”, the flip-flop FF1 senses and latches thevoltage of the node N1, write data is maintained at “1”. In the datacircuit storing write data of “2”, whether or not data in thecorresponding memory cell has been sufficiently brought to the state forwriting “2” is detected. If data in the-memory cell is “2”, theflip-flop FF1 senses and latches the voltage of the node N1 so thatwrite data is changed to “0”. If data in the memory cell is not “2”, theflip-flop FF1 senses and latches the voltage of the node N1 so thatwrite data is maintained at “2”. Write data in the data circuit storingwrite data “0” is not changed.

[0568] During the write verification, the signal VRFYBB is made to be“H” and the voltage VS is made to be 0V.

[0569] If all of the selected memory cells for writing “1” or “2” havereached a required threshold voltage, the nodes N4 of all of the datacircuits are made to be “L”. That is, when data has been sufficientlywritten to all of the selected memory cells for writing “1” or “2”, thenodes N3 of all of the data circuits 206-0, 206-1, 206-m-1 and 206-m aremade to be “H”. On the other hand, node N4 of the same is made to be“L”. If the foregoing facts are detected, whether or not all of theselected memory cell for writing “2” or “3” have reached a requiredthreshold voltage can be detected. Completion of writing of “2” and “3”can be detected by using a transistor Qn5 for simultaneously detectingwriting “2” and “3”, as shown in FIG. 40. After the verify readoperation has been completed, VRT is precharged to, for example, Vcc. Ifone or more memory cells in which “1” or “2” has been writteninsufficiently exists, the node N4 of the data circuit is “H”.Therefore, the n-channel MOS transistor Qn5 is turned on so that VRT isgrounded. After data has been sufficiently written on all of the memorycells for writing “1” or “2”, the nodes N4 of the data circuits 206-0,206-1, . . . , 206-m-1 and 206-m are made to be “L”. As a result, then-channel MOS transistors Qn5 in all of the data circuits are turnedoff. Thus, VRT holds the precharged potential.

[0570] The multilevel storing NAND type EEPROM according to the sixthembodiment has the structure such that one or more bit line voltagecontroller electrically charge the bit line to a required bit line writecontrol voltage when data is written. The apparatus according to thisembodiment is able to realize a bit line voltage controller having asimple structure and capable of applying a bit line write controlvoltage corresponding to n(n≧2)-level write data to the bit line.

[0571] Therefore, the size of the column-system circuit 3 can be reducedbecause the number of the sense amplifier circuits, data latch circuitsand verifying circuits. Therefore, a nonvolatile semiconductor memorydevice capable of realizing a highly integrated structure can beobtained.

[0572] (Seventh Embodiment)

[0573] A multilevel storing NAND type EEPROM according to a seventhembodiment of the present invention will now be described.

[0574] Although the EEPROM according to the sixth embodiment has thestructure for ternary-level is treated as the number of the multileveldata, the EEPROM according to the seventh embodiment has a structuresuch that the number of the multilevel data is four.

[0575] The EEPROM according to the seventh embodiment has a structuresimilar to that according to the sixth embodiment shown in FIGS. 36 and37.

[0576]FIG. 46 is a graph showing distribution of threshold voltage of amemory cell transistor when four-levels are stored.

[0577] When the EEPROM is structure to be capable of storingfour-levels, four writing states are provided for one memory celltransistor M. The four writing states are distinguished from one anotherin accordance in with the threshold voltage of the memory celltransistor M.

[0578] As shown in FIG. 46, the state of data “0” in the EEPROM havingthe power supply voltage Vcc which is set to 3V is made to be the sameas the state-after data has been erased. Thus, for example, a negativethreshold voltage is assigned. In a state of data “1”, a thresholdvoltage from, for example, 0.5V to 0.8V is assigned. In a state of data“2”, a threshold voltage from, for example, 1.5V to 1.8V is assigned. Ina state of data “3”, a threshold voltage from, for example, 2.5V to 2.8Vis assigned.

[0579] When data is read from the memory cell transistor M, three readvoltages VCG2R, VCG3R and VCG1R are applied to the control gate CG.

[0580] Initially, reading voltage VCG2R is applied to the control gateCG. In accordance with whether the memory cell transistor M turns on oroff, whether stored data is “0, 1” or “2, 3” is detected. Then, readingvoltage VCG3R is applied so that whether stored data is “2” or “3” isdetected. When reading voltage VCG1R is applied, whether data is “0” or“1” is detected. The reading voltages VCG1R, VCG2R and VCG3R are, forexample, 0V, 1V and 2V, respectively.

[0581] Voltages VCG1V, VCG2V and VCG3V are voltages called verify readvoltages which are used to detect (when a verifying operation isperformed) whether or not data has been sufficiently written. The verifyread voltage is applied to the control gate CG after data has beenwritten. Whether or not the threshold voltage of the memory celltransistor M has been shifted to a range corresponding to written datacan be detected in accordance with whether or not the memory celltransistor M is turned on when the verify read voltage has been appliedto the control gate CG. By using this, whether or not sufficient writinghas been performed is detected. The verify read voltages VCG1V, VCG2Vand VCG3V are, for example, 0.5V, 1.5V and 2.5V, respectively.

[0582]FIG. 47 is a circuit diagram of a data circuit 206B of the EEPROMaccording to the seventh embodiment of the present invention. The datacircuit 206B shown in FIG. 47 is arranged to store four-level data.

[0583] As shown in FIG. 47, write/read data is latched by a flip-flopFF1 formed of n-channel MOS transistors Qn21, Qn22 and Qn23 andp-channel MOS transistors Qp9, Qp10 and Qp11 and a flip-flop FF2 formedof n-channel MOS transistors Qn29, Qn30 and Qn31 and p-channel MOStransistors Qp16, Qp17 and Qp18. The foregoing flip-flops FF1 and FF2serve as sense amplifiers.

[0584] The flip-flops FF1 and FF2 latches whether “0” is written,whether “1” is written, whether “2” is written or whether “3” is writtenas write data information and senses and latches whether the memory cellhas information of “0”, information of “1”, information of “2” orinformation of “3” as read data information.

[0585] The data input/output lines I/OA and I/OB and the flip-flop FF1are connected to each other through the n-channel MOS transistors Qn28and Qn27. The data input/output lines I/OC and I/OD and the flip-flopFF2 are connected to each other through the n-channel MOS transistorsQn35 and Qn36. The data input/output lines I/OA, I/OB, I/OC and I/OD arealso connected to the data input/output buffer 205 shown in FIG. 36.

[0586] The gates of the n-channel MOS transistors Qn27, Qn28, Qn35 andQn36 are connected to the output of a column address decoder formed of aNAND logic circuit G2 and an inverter I4. The n-channel MOS transistorsQn26 and Qn34 equalize flip-flops FF1 and FF2 when signals ECH1 and ECH2are “H”. The n-channel MOS transistors Qn24 and Qn32 control theconnection between the flip-flops FF1 and FF2 and a MOS capacitor Qd1.The n-channel MOS transistors Qn25 and Qn33 control the connectionbetween the flip-flops FF1 and FF2 and a MOS capacitor Qd2.

[0587] A circuit formed of the p-channel MOS transistors Qp12 and Qp13changes the gate voltage of the MOS transistor Qd1 in response toactivating signal VRFYBA and in accordance with data in the flip-flopFF1. A circuit formed of the p-channel MOS transistor Qp14 and Qp15changes the gate voltage of the MOS capacitor Qd2 in accordance withdata in the flip-flop FF1 and in response to activating signal VRFYBB. Acircuit formed of the n-channel MOS transistors Qn1 and Qn2 changes thegate voltage of the MOS capacitor Qd1 in accordance with data in theflip-flop FF2 and in response to activating signal RRFYBA1. A circuitformed of the n-channel MOS transistors Qn3 and Qn4 changes the gatevoltage of the MOS capacitor Qd2 in accordance with data in theflip-flop FF2 and in response to activating signal VRFYBB1.

[0588] Each of the MOS capacitors Qd1 and Qd2 comprises a depletionn-channel MOS transistor and has a capacity which issufficiently-smaller than the capacity of the bit line. The n-channelMOS transistor Qn37 electrically charges the MOS capacitor Qd1 inresponse to signal PREA. The n-channel MOS transistor Qn38 electricallycharges the MOS capacitor Qd2 to voltage VB in response to signal PREB.The n-channel MOS transistors Qn39 and Qn40 control the connectionbetween the data circuit 206B and the bit lines B1a and B1b in responseto signals BLCA and BLCB. A circuit formed of the n-channel MOStransistors Qn37 and Qn38 also serves as a bit line voltage controller.A circuit formed of the p-channel MOS transistors Qp12 and QP13, acircuit formed of the p-channel MOS transistors Qp14 and Qp15, a circuitformed of the n-channel MOS transistors Qn1 and Qn2 and a circuit formedof the n-channel MOS transistors Qn3 and Qn4 also serve as bit linevoltage controllers.

[0589] The operation of the EEPROM having the above-mentioned structurewill now be described with reference to the operation waveform. In thefollowing description, a state where control gate CG2A has been selectedwill now be described.

[0590] Reading Operation

[0591]FIG. 48 is an operation waveform showing a reading operation.

[0592] As shown in FIG. 48, at time t_(1R), voltages VA and VBrespectively are made to be 1.8V and 1.5V so that bit lines BLa and BLbrespectively are made to be 1.8V and 1.5V. When signals BLCA and BLCBare made to be “L” and the bit line BLa and the MOS capacitor Qd1 areseparated from each other and the bit line BLb and the MOS capacitor Qd2are separated from each other. Moreover, the bit lines BLa and BLb arebrought to a floating state. When the signals PREA and PREB are made tobe “L”, the nodes N1 and N2 which are the gate electrodes of the MOScapacitors Qd1 and Qd2 are brought to a floating state. At time t_(2R),the selected control gate CG2A in a block selected by the controlgate/selection gate driver 202B is made to be 1V, and the non-selectedcontrol gates CG1A, CG3A and CG4A and the selection gates SG1A and SG2Aare made to be Vcc. If the threshold voltage of the selected memory cellis 1V or lower, the bit line voltage is made to be lower than 1.5V. Ifthe threshold voltage of the selected memory cell is 1V or higher, thebit line voltage is maintained at 1.8V. Then, at time t_(3R), thesignals BLCA and BLCB are made to be “H” so that data in the bit line istransferred to the MOS capacitors Qd1 and Qd2. Then, the signals BLCAand BLCB are again made to be “L” so that the bit line B1a and the MOScapacitor Qd1 are separated from each other and the bit line BLb and theMOS capacitor Qd2 are separated from each other. When the signals SAN1and SAP1 respectively are made to be “L” and “H” so that the flip-flopFF1 is deactivated. When the signal ECH1 is made to be “H” so as to beequalized. Then, the signal RV1A and RV1B are made to be “H”. At timet_(4R), the signals SAN1 and SAP1 respectively are made to be “H” and“L” so that the voltages of the nodes N1 and N2 are sensed and latched.As a result, data in the memory cell is sensed whether it is “0” or “1”;or “2” or “3” by the flip-flop FF1 and information of this is latched.

[0593] Then, the selected control gate CG2A is made to be 2V. At timet_(5R), the signals PREA and PREB are made to be “H” so that the nodesN1 and N2 which are gate electrodes of the MOS capacitors Qd1 and Qd2respectively are made to be 1.8V and 1.5V. When the signals PREA andPREB are made to be “L”, the nodes N1 and N2 which are gate electrodesof the MOS capacitors Qd1 and Qd2 are brought to a floating state. Ifthe threshold voltage of the selected memory cell is 2V or lower, thebit line voltage is made to be 1.5V or lower. If the threshold voltageof the selected memory cell is 2V or higher, the bit line voltage ismaintained at 1.8V. Then, at time t_(6R), signals BLCA and BLCB are madeto be “H”. The signals BLCA and BLCB are again made to be “L” so thatthe bit line Bla and the MOS capacitor Qd1 are separated from each otherand the bit line BLb and the MOS capacitor Qd2 are separated from eachother. When the signals SAN2 and SAP2 are brought to “L” level so thatthe bit line B1a and the MOS capacitor Qd1 are separated from each otherand the bit line BLb and the MOS capacitor Qd2 are separated from eachother. When the signals SAN2 and SAP2 respectively are brought to “L”and “H” so that the flip-flop FF2 is deactivated. When the signal ECH2is made to be “H” so as to be equalized. Then, the signal RV2A and RV2Bare made to be “H”. At time t_(7R), the signals SAN2 and SAP2respectively are made to be “H” and “L” so that the voltage of the nodeN1 is sensed and latched. Thus, whether or not data in the memory cellis “3” is sensed by the flip-flop FF2 and information of this islatched.

[0594]FIG. 49 is a is table showing read data sensed and latched by theflip-flops FF1 and FF2 at time t_(7R).

[0595] Finally whether or not data written in the memory cell is “0” issensed. At time t_(8R), the bit lines BLa and BLb respectively areelectrically charged to 1.8V and 1.5V, and then brought to a floatingstate. Also the nodes N1 and N2 which are the gate electrodes of the MOScapacitors Qd1 and Qd2 are brought to a floating state. Then, at timet_(9R), the selected control gate CG2A in the block selected by thecontrol gate/selection gate driver 202B is made to be 0V and thenon-selected control gates CG1A, CG3A and CG4A and the selection gatesSG1A and SG2A are made to be Vcc. If the threshold voltage of theselected memory cell is 0V or lower, the bit line voltage is made to be1.5V or lower. If the threshold voltage of the selected memory cell is0V or higher, the bit line voltage is maintained at 1.8V.

[0596] At time t_(10R), signals BLCA and BLCB are made to be “H” so thatdata in the bit line is transferred to the MOS capacitors Qd1 and Qd2.Then, the signals BLCA and BLCB are again made to be “L” so that the bitline B1a and the MOS capacitor Qd1 are separated from each other and thebit line BLb and the MOS capacitor Qd2 are separated from each other.Prior to sensing data in the MOS capacitor, VRFYBA1 is made to be Vcc attime t_(11R).

[0597] As can be understood from FIG. 49, the node N5 is made to be “H”only when data is “3”. Therefore, only when data is “3”, the n-channelMOS transistor Qn2 is turned on so that the node N1 is grounded. Whenthe signals SAN2 and SAP2 respectively are made to be “L” and “H” sothat the flip-flop FF2 is deactivated. When the signal ECH2 is made tobe “H” so as to be equalized. Then, the signals RV2A and RV2B are madeto be “H”.

[0598] At time t_(12R), the signals SAN2 and SAP2 respectively are madeto be “H” and “L” so that the voltage of the node N1 is sensed andlatched. Thus, whether or not data in the memory cell is “0” is sensedby the flip-flop FF2 and information of this is latched.

[0599]FIG. 50 is a table showing read data which is sensed and latchedby the flip-flops FF1 and FF2.

[0600] As a result of the foregoing reading operation, four-level datais latched by the flip-flops FF1 and FF2, as shown in FIG. 50.

[0601] Data items shown in FIG. 50 have threshold voltages distributedas follows:

[0602] data “0”: threshold voltage is 0V or lower

[0603] data “1”: threshold voltage is 0.5V or higher and 0.8V or lower

[0604] data “2”: threshold voltage is 1.5V or higher and 1.8V or lower

[0605] data “3”: threshold voltage is 2.5V or higher and 2.8V or lower

[0606] During the reading operation, the signals VRFYBA and VRFYBB are“H” level. Moreover, the voltage Vs (Vsa, Vsb) is made to be 0V.

[0607] When the column activating signal CENB to be supplied to thecolumn address decoder is made to be “H”, data stored in the datacircuit selected by the address signal is output to the datainput/output lines I/OA, I/OB, I/OC and I/OD so as to be output to theoutside of the EEPROM through the data input/output buffer 205.

[0608] The relationship among data stored in the memory cell, thethreshold voltage and levels to be output to the data input/output linesI/OA, I/OB, I/OC and I/OD after data has been read is as shown in FIG.50.

[0609] Data to be output to the outside of the chip may be data obtainedby converting signals output to the data input/output lines I/OA, I/OB,I/OC and I/OD by the data input/output buffer 205.

[0610] Writing Operation

[0611]FIG. 51 is a flow chart schematically showing the writingoperation.

[0612] In step #2, write data is loaded into the flip-flops FF1 and FF2.

[0613] In step #4, data “2” and “3” are substantially simultaneouslywritten in the program first cycle.

[0614] In step #6, a verify read first cycle is performed to detectwhether or not data “2” and “3” have been sufficiently written. Ifmemory cell to which data has not been sufficiently written exists,writing is again performed (steps #8 and #10).

[0615] When data has been sufficiently written in all of the memorycells for writing data “2” and “3”, data is, in step #12, writtensubstantially simultaneously in the memory cell for writing data “1”(program second cycle). In step #14, a verify second cycle is performedto detect whether or not data “1” has been sufficiently written. Data isagain written to a memory cell to which data “1” has not beensufficiently written (steps #16 and #18). When data has beensufficiently written in all of the memory cells, writing is ended.

[0616] The program first cycle, the verify read first cycle, the programsecond cycle and the verify read second cycle will sequentially bedescribed.

[0617] (1) Program First Cycle

[0618] Prior to performing the writing operation, supplied data for twobits is converted by the data input/output buffer 4 so as to be suppliedto the data circuit 206B.

[0619]FIG. 52 is a table showing write data to be supplied to the datacircuit 206B and latched by the flip-flops FF1 and FF2. The relationshipbetween the four-level data and the data input/output lines I/OA, I/OB,I/OC and I/OD is as shown in FIG. 52.

[0620] Converted four-level data is transferred to a data circuit at acolumn address instructed with the address signal when the columnactivating signal CENB is “H”.

[0621]FIG. 53 is an operation waveform showing the writing operation(the program first cycle).

[0622] At time t_(1w), voltage VA is made to be the bit line writingcontrol voltage 1V so that the bit line BLa is made to be 1V. Whenvoltage drop of the n-channel MOS transistor Qn39 corresponding to thethreshold voltage raises a problem, the level of the signal BLCA isrequired to be raised. Then, the signal PRE is made to be “L” so thatthe bit line is brought to a floating state. At time t_(2w), the signalRV2A is made to be 1.5V. As a result, bit line control voltage of 0V isapplied to the bit line of the columns having data “1” or “3”. When thethreshold voltage of the n-channel MOS transistor Qn32 is made to be 1V,the n-channel MOS transistor Qn32 is turned off when “0” or “2” iswritten. When “1” or “3” is written, the n-channel MOS transistor Qn32is turned on. Then, VRFYBA is made to be 0V at time t_(3w), and bit linewrite control voltage Vcc is output from a data circuit having data “0”or “1” to the bit line.

[0623] As a result, bit lines for writing “0” or “1” are made to be Vcc,bit line for writing “2” are made to be 1V and bit lines for writing “3”are made to be 0V.

[0624] At time t_(1w), selection gate SG1A and control gates CG1A toCG4A of the block selected by the control gate/selection gate driver202B are made to be Vcc. The selection gate SG2A is made to be 0V. Then,the selected control gate CG2A is made to be high voltage of VPP (forexample, 20V), while the non-selected control gates CG1A, CG3A and CG4Aare made to VM (for example, 10V). In the memory cell corresponding to adata circuit storing data “3”, the difference in the potential betweenthe channel potential of 0V and VPP of the control gate causes electronsto be injected into the floating gate so that the threshold voltage isincreased. In the memory cell corresponding to the data circuit storingdata “2”, the difference in the potential between the channel potentialof 1V and VPP of the control gate causes electrons to be injected intothe floating gate so that the threshold voltage is increased. The reasonwhy the channel potential is made to be 1V is that the quantity ofelectrons may be smaller as compared with the case in which data “3” iswritten. In the memory cell corresponding to the data circuit storingdata “0” or “1”, the difference in the potential between the channelpotential and VPP of the control gate is small. Therefore, substantiallyno electrons is injected into the floating gate. Therefore, thethreshold voltage of the memory cell is not changed. During the writingoperation, signals SAN1, SAN2, VRFYBB, PREB and BLCB are “H” level,signals SAP1, SAP2, RV1A, RV1B, RV2B, ECH1 and ECH2 are “L” level andthe voltage VB is 0V.

[0625] (2) Verify Reading First Cycle

[0626] After the writing operation has been completed, the thresholdvoltages of the memory cell for writing “2” and that for writing “3” aredetected (verification of writing). If a required threshold voltage hasbeen realized, data in the data circuit is changed to “0”. If therequired threshold voltage has not been realized, data in the datacircuit is maintained and writing is again performed. The program firstcycle and write verify first cycle are repeated until all of the memorycells for writing “2” and those for writing “3” reach required thresholdvoltages.

[0627]FIG. 54 an operation waveform showing the verify reading operation(verify read first cycle).

[0628] At time t_(1V), voltages VA and VB respectively are made to be1.8V and 1.5V so that the bit lines BLa and BLb are made to be 1.8V and1.5V. The signals BLCA and BLCB are made to be “L” so that the bit lineBla and the MOS capacitor Qd1 are separated from each other and the bitline BLb and the MOS capacitor Qd2 are separated from each other. Thus,the bit lines BLa and BLb are brought to a floating state. When signalsPREA and PREB are made to be “L” so that the nodes N1 and N2 which arethe gate electrodes of the MOS capacitors Qd1 and Qd2 are brought to afloating state. At time t2V, the selected control gate CG2A in the blockselected by the control gate/selection gate driver 202B is made to be1.5V, the non-selected control gates CG1A, CG3A and CG4A and theselection gates SG1A and SG2A are made to be Vcc. If the thresholdvoltage of the selected memory cell is 1.5V or lower, the bit linevoltage is made to be lower than 1.5V. If the threshold voltage of theselected memory cell is 1.5V or higher, the bit line voltage ismaintained at 1.8V.

[0629] At time t_(3v), the signals BLCA and BLCB are made to be “H” sothat the potential of the bit line is transferred to the nodes N1 andN2. Then, the signals BLCA and BLCB are made to be “L” so that the bitline Bla and the MOS capacitor Qd1 are separated from each other and thebit line BLb and the MOS capacitor Qd2 are separated from each other. Attime t_(4v), the signal RV2A is made to be, for example, 1.5V which isnot higher than Vcc. If the threshold voltage of the n-channel MOStransistor Qn32 is 1V, the n-channel MOS transistor Qn32 in the datacircuit storing write data “3” is turned on so that the node N1 is madeto be 0V. If “2” has been sufficiently written in the memory cell in thedata circuit storing write data “2”, the n-channel MOS transistor Qn32is turned off so that the node N1 is maintained at 1.5V or higher. Ifwriting of “2” is insufficient, the node N1 is 1.5V or lower.

[0630] When the signal VRFYBA has been made to be “L” at time t_(5v),the p-channel MOS transistor Qp13 in the data circuit storing write data“0” or “1” is turned on so that the node N1 is made to be Vcc. Thesignals SAN1 and SAP1 respectively are made to be “L” and “H” so thatthe flip-flop FF1 is deactivated so that the signal ECH1 is made to be“H” so as to be equalized. Then, signals RV1A and RV1B are made to be“H”. When the signals SAN1 and SAP1 are again made to be “H” and “L”,the voltage of the node N1 is sensed and latched at time t_(6V). Then,whether or not data in the memory cell corresponding to the data circuitstoring write data “2” has been sufficiently brought to the state forwriting “2” is detected. If data in the memory cell is “2”, theflip-flop FF1 senses and latches the voltage of the node N1 so thatwrite data is changed to “0”. If data in the memory cell is not “2”, theflip-flop FF1 senses and latches the voltage of the node N1 so thatwrite data is maintained at “2”. Write data for the data circuit storingwrite data “0” or “1” or “3” is not changed.

[0631] Then, the selected control gate is made to be 2.5V. If thethreshold voltage of the selected memory cell is 2.5V or lower, the bitline voltage is made to be lower than 1.5V. If the threshold voltage ofthe selected memory cell is 2.5V or higher, the bit line voltage ismaintained at 1.8V. At time t_(7v), signals BLCA and BLCB are made to be“H” so that the potential of the bit line is transferred to the nodes N1and N2. The signals BLCA and BLCB are again made to be “L” so that thebit line Bla and the MOS capacitor Qd1 are separated from each other andthe bit line BLb and the MOS capacitor Qd2 are separated from eachother. When the signal VREYBC is then made to be “L”, the p-channel MOStransistor Qp12c of a data circuit storing write data “0” or “1” and adata circuit on which “2” has been sufficiently written is turned on sothat the node N1 is made to be Vcc. When the signals SAN1 and SAP1 aremade to be “L” and “H”, the flip-flop FF1 is deactivated so that thesignal ECH1 is made to be “H” so as to be equalized. Then, the signalsRV1A and RV1B respectively are made to be “H” and “L” so that thevoltage of the node N1 is sensed and latched.

[0632] Then, as shown in FIG. 54, write data is changed. At time t_(9v),the signals BLCA and BLCB are made to be “H” so that the potential ofthe bit line is transferred to the nodes N1 and N2. The signals BLCA andBLCB are again made to be “L” so that the bit line Bla and the MOScapacitor Qd1 are separated from each other and the bit line BLb and theMOS capacitor Qd2 are separated from each other. At time t_(10V) , theVRFYBA1 is made to be “H” so that the n-channel MOS transistor Qn2 inthe data circuit storing write data “0” or “2” is turned on so that thenode N1 is made to be Vcc. The signals SAN2 and SAP2 respectively aremade to be “L” and “H” so that the flip-flop FF2 is deactivated and thesignal ECH2 is made to be “H” so as to be equalized. Then, the signalsRV2A and RV2B are made to be “H”. At time t_(11v), the signals SAN2 andSAP2 are made to be “H” and “L” so that the voltage of the node N1 issensed and latched.

[0633] In the seventh embodiment, VRFYBA1 is made to be Vcc at timet_(10v), the node N1 of the MOS capacitor Qd1 is electrically charged tobe higher than the potential (1.5V) of the node N2 in a case where “0”or “2” is written. The signal RV2B may be made to be, for example, 1.5Vat time t_(10v). When data “0” is written or data “2” is written in theforegoing case, the node N6 is 0V so that the n-channel MOS transistorQn33 is turned on so that the node N2 is made to be 0V. When “1” or “3”is written, the node N6 is made to be Vcc and the node N2 is made to be1.5V so that the n-channel MOS transistor Qn33 is turned off. Thus, thenode N2 can be maintained at 1.5V. At time t_(10v), the VRFYBA1 is madeto be Vcc. Since charging of the node N1 when “0” or “2” is written isrequired to be higher than the potential (0V) of the node N2, lowvoltage of about 0.5V is sufficient to electrically charge the node N1.

[0634] As described above, it is detected whether or not data in thememory cell corresponding to the data circuit storing write data “3” hasbeen sufficiently brought to a state for writing “3”. If data in thememory cell is “3”, the flip-flops FF1 and FF2 sense and latch thevoltage of the node N1 so that write data is changed to “0”. If data inthe memory cell is not “3”, the flip-flops FF1 and FF2 sense and latchthe voltage of the node N1 so that write data “3” is maintained. Writedata of the data circuit storing write data “0” or “1” or “2” is notchanged.

[0635] During the write verification, the signal VRFYBB is made to be“H” and the voltage VS is made to be 0V.

[0636]FIG. 55 is a table showing data latched by the flip-flops FF1 andFF2 after data “2” or “3” has been sufficiently written.

[0637] If all of the selected memory cells for writing “2” or “3” havereached a required threshold voltage, data in the data circuits are asshown in FIG. 55. That is, when data has been sufficiently written toall of the selected memory cells for writing “2” or “3”, the nodes N3 ofall of the data circuits 206B-0, 206B-1, . . . , 206N-m-1 and 206B-m aremade to be “H”. On the other hand, node N4 of the same is made to be“L”. If the foregoing facts are detected, it can be determined whetheror not all of the selected memory cell for writing “2” or “3” havereached a required threshold voltage.

[0638]FIG. 56 is a diagram showing a modification of the data circuitand is a circuit diagram showing a data circuit 206C having a writecompletion simultaneously detecting transistor.

[0639] Completion of writing of “2” and “3” can be detected by using atransistor Qn5 for simultaneously detecting writing “2” and “3”structured as shown in FIG. 56. After the verify read first cycle hasbeen completed, VRT is precharged to, for example, Vcc. If one or morememory cells in which “2” or “3” has been written insufficiently exists,the node N4 of the data circuit is “H”. Therefore, the n-channel MOStransistor Qn5 is turned on so that VRT is grounded. After data has beensufficiently written on all of the memory cells for writing “2” or “3”,the nodes N4 of the data circuits 206C-0, 206C-1, . . . , 206C-m-1 and206C-m are made to be “L”. As a result, the n-channel MOS transistorsQn5 in all of the data circuits are turned off. Thus, VRT holds theprecharged potential.

[0640] (3) Program Second Cycle

[0641] After writing of “2” and “3” has been completed, writing of “1”(program second cycle) is performed. The node potential of the flip-flopwhen “1” is written is as shown in FIG. 55. That is, when “1” is written, the node N5 is made to be “L” so that the writing potential is appliedto the bit line. When data except for “1” is written, the node N5 ismade to be “H” so that the write non-selected potential is applied tothe bit line.

[0642]FIG. 57 is an operation waveform showing the writing operation(the program second cycle).

[0643] At time t_(1p), the voltage VRFYBA1 is made to be “H” so that thebit line Bla for writing “0” or “2” or “3” is electrically charged tothe write non-selected voltage Vcc. When the degree of voltage dropcorresponding to the threshold voltage of the n-channel MOS transistorQn39 raises a problem, the level of the signal BLCA is required to beraised. Then, the signal RV2A is made to be Vcc. As a result, writenon-selected voltage Vcc is applied from a data circuit storing data “0”or “2” or “3” to the bit line BLa. A write bit line potential of 0V isapplied to the bit line Bla from a data circuit storing data “1”.

[0644] The selection gates SG1A and CG1A to CG4A in the block selectedby the control gate/selection gate driver 202B are made to be Vcc. Theselection gate SG2A is 0V. At time t_(2p), the selected control gateCG2A is made to be high voltage of VPP (for example, 20V), and thenon-selected control gate CG1A, CG3A and CG4A are made to theintermediate voltage VM (for example, 10V). In the memory cellcorresponding to the data circuit storing data “1”, the potentialdifference between the channel potential of 0V and VPP of the controlgate causes electrons to be injected into the floating gate so that thethreshold voltage is increased. In the memory cell corresponding to thedata circuit storing data “0” or “2” or “3”, the small difference in thepotential between the channel potential and VPP of the control gatesubstantially prevent injection of electrons into the floating gate.Therefore, the threshold voltage of the memory cell is not changed.During the writing operation, signals SAN1, SAN2, VRFYBB, PREB and BLCBare made to be “H”, signals SAP1, SAP2, RV1A, RV1B, ECH1 and ECH2 aremade to be “L” and the voltage VB is made to be V.

[0645] (4) Verify Read Second Cycle

[0646] After program second cycle has been completed, the thresholdvoltage of the memory cell in which “1” is written is detected (writeverify second cycle). If it has reached a predetermined thresholdvoltages, data in the data circuit is changed to “0”. If it has notreached the required threshold voltage, data in the data circuit ismaintained and writing is again performed. The writing and write verifyoperations are repeated until all of the memory cells, on which “1” iswritten, reach required threshold voltages.

[0647]FIG. 58 is an operation waveform showing the verify read operation(verify read second cycle).

[0648] At time t_(1y), voltage VA and VB respectively are made to be1.8V and 1.5V so that bit lines BLa and BLb respectively are made to be1.8V and 1.5V. When signals BLCA and BLCB are made to be “L”, the bitline BLa and the MOS capacitor Qd1 are separated from each other and thebit line BLb and the MOS capacitor Qd2 are separated from each other.Moreover, the bit line BLa and BLb are brought to a floating state. Whenthe signals PREA and PREB are made to be “L”, the nodes N1 and N2 whichare the gate electrodes of the MOS capacitors Qd1 and Qd2 are brought toa floating state.

[0649] At time t_(2y), the selected control gate CG2A in a blockselected by the control gate/selection gate driver 202B is made to be0.5V, and the non-selected control gates CG1A, CG3A and CG4A and theselection gates SG1A and SG2A are made to be Vcc. If the thresholdvoltage of the selected memory cell is 0.5V or lower, the bit linevoltage is made to be lower than 1.5V. If the threshold voltage of theselected memory cell is 0.5V or higher, the bit line voltage ismaintained at 1.8V.

[0650] Then, at time t_(3y), the signals BLCA and BLCB are made to be“H” so that the potential of the bit line is transferred to the nodes N1and N2. Then, the signals BLCA and BLCB are made to be “L” so that thebit line Bla and the MOS capacitor Qd1 are separated from each other andthe bit line BLb and the MOS capacitor Qd2 are separated from eachother.

[0651] When the VRFYBA1 has been made to be “H” at time t_(4y), then-channel MOS transistor Qn2 in the data circuit storing write data “0”or “2” or “3” is turned on so that the node N1 is made to be Vcc.

[0652] When the signals SAN2 and SAP2 respectively are made to be “L”and “H” so that the flip-flop FF2 is deactivated. When the signal ECH2has been made to be “H”, it is equalized. Then, the signals RV2A andRV2B are made to be “H”.

[0653] When the signals SAN2 and SAP2 respectively are again made to be“H” and “L”, the voltage of the node N1 is sensed and latched at timet_(5y). Thus, it is determined whether or not data in the memory cellcorresponding to only the data circuit storing write data “1” has beensufficiently brought to the state for writing “1”. If data in the memorycell is “1”, the voltage of the node N1 is sensed and latched by theflip-flop FF2 so that the write data is changed to “0”. If data in thememory cell is not “1”, the flip-flop FF1 senses and latches the voltageof the node N2 so that the write data “1” is maintained. Write data inthe data circuit storing write data “0” or “2” or “3” is not changed.

[0654]FIG. 59 is a table showing data latched by the flip-flops FF1 andFF2 after data “3” has been sufficiently written.

[0655] If all of the selected memory cells for writing data “1” havereached desired threshold voltages, data in the data circuit is as shownin FIG. 59. That is, if data has been sufficiently written in all of thememory cell for writing data “1”, the node N5 of all of the datacircuits 206C-0, 206C-1, . . . , 206C-m-1 and 206C-m are made to be “H”.Moreover, the nodes N6 of the same are made to be “L”. By detecting theforegoing facts, it can be determined whether or not all of the selectedmemory cells have reached the required threshold voltages.

[0656] The program second cycle write completion can be detected byusing the write completion simultaneously detecting transistor Qn6formed, for example, as shown in FIG. 56. The signal VRED is prechargedto, for example, Vcc after the verify read second cycle has beencompleted. If one or more memory cell in which data “1” has not beensufficiently written exists, the n-channel MOS transistor Qn6 is turnedon and VRED is grounded because the node N6 of the data circuit is “H”.If data has been sufficiently written in all-of the memory cells, thenodes N6 of the data circuits 206C-0, 206C-1, 206C-m-1 and 206C-m aremade to be “L”. As a result, the n-channel MOS transistors Qn6 in all ofthe data circuits are turned off and the signal VRED maintains theprecharged potential.

[0657] The EEPROM according to the seventh embodiment is structured asdescribed above. The verify reading, writing and usual reading are notlimited to the foregoing operation examples. Other examples may beemployed.

[0658]FIG. 60 is an operation waveform showing another verify readoperation (verify read first cycle).

[0659] The verify read first cycle may be structured, for example, asshown in the operation waveform shown in FIG. 60.

[0660] In the verify read first cycle shown in FIG. 60, the operation totime t_(7v) is the same as the verify read first cycle shown in FIG. 54.The operation is different from the same from time t_(7v).

[0661] At time t_(7v), the signals BLCA and BLCB are made to be “H”, andthe potential of the bit line is transferred to the nodes N1 and N2. Ifthe threshold voltage of the memory cell is 2.5V or higher, the bit lineBla is 1.5V or higher. If the threshold voltage of the memory cell is2.5V or lower, the bit line BLb is 1.5V or lower. Then, the signals BLCAand BLCB are made to be “L” so that the bit line Bla and the MOScapacitor Qd1 are separated from each other and the bit line BLb and theMOS capacitor Qd2 are separated from each other. When the signal VRFYBAhas been made to be “H” at time t_(8z), the n-channel MOS transistor Qn2of the data circuit storing write data “0” or “2” is turned on.Therefore, the node N1 is made to be 1.5V or higher. When the signalsSAN2 and SAP2 have respectively been made to be “L” and “H”, theflip-flop FF2 is deactivated so that the signal ECH2 is made to be “H”and equalized. Then, the signals RV2A and RV2B are made to be “H”. Whenthe signals SAN2 and SAP2 have respectively been made to be “H” and “L”at time t_(9z), the voltage of the node N1 is sensed and latched.

[0662] Then, write data is changed, as shown in FIG. 60. At timet_(10z), the signals BLCA and BLCB are made to be “H” so that thepotential of the bit line is transferred to the nodes N1 and N2. Then,the signals BLCA and BLCB are again made to be “L” so that the bit lineBla and the MOS capacitor Qd1 are separated from each other and the bitline BLb and the MOS capacitor Qd2 are separated from each other.

[0663] When the signal VRFYBA has been made to be “L” at time t_(11z),the p-channel MOS transistor Qp13 of the data circuit storing write data“0” or “1” and the data circuit on which data “2” has been sufficientlywritten is turned on and the node N1 is made to be Vcc. The signals SAN1and SAP1 respectively are made to be “L” and “H” so that the flip-flopFF1 is deactivated, and the signal ECH1 is made to be “H” and equalized.Then, the signal RV1A and RV1B are made to be “H”. When the signals SAN1and SAP1 respectively are made to be “H” and “L” at time t_(12z), thevoltage of the node N1 is sensed and latched.

[0664] As described above, it can be determined whether or not data inthe memory cell corresponding to only the data circuit storing writedata “3” has been sufficiently brought to the state for writing “3”. Ifdata in the memory cell is “3”, the flip-flops FF1 and FF2 sense andlatch the voltage of the node N1 so that write data is changed to “0”.If data in the memory cell is not “3”, flip-flops FF1 and FF2 sense andlatch the voltage of the node N1 so that write data is maintained at“3”. Write data in the data circuit storing write data “0” or “1” or “2”is not changed. If all of the selected memory cells for writing “2” or“3” have reached desired threshold voltages, data in the data circuit ismade as shown in FIG. 55. That is, when data has been sufficientlywritten in all of the selected memory cells for writing “2” or “3”,nodes N3 of all of the data circuits 206C-0, 206C-1, 206C-m-1 and 206C-mare made to be “H” and nodes N4 of the same are made to be “L”. Bydetecting this, it can be determined whether or not all of the selectedmemory cells for writing “2” or “3” have reached required thresholdvoltages.

[0665] The circuit structure of the data circuit 206 is not limited tothe data circuits 206B and 206C shown in FIGS. 47 and 56. Anothercircuit structure may be employed.

[0666]FIGS. 61 and 62 are circuit diagrams showing another structure ofthe data circuit.

[0667] The operation timing of the signals VRFYBA1 and VRFYBB1 for thedata circuit 206D shown in FIG. 61 may be determined such that Vcc ismade to be 0v and 0V is made to be Vcc when a similar operation timingfor the data circuits shown in FIGS. 47 and 56 is employed (operationwaveforms shown in FIGS. 48, 53, 54, 57, 48 and 60). Note that theoperation timings of the signals VRFYBA and VRFYBB are similar to thosein the case where the data circuits shown in FIG. 47 and 56 areemployed.

[0668] The operation timing of the signals VRFYBA and VRFYBB for thedata circuit 206E shown in FIG. 62 may be determined such that Vcc ismade to be 0v and 0V is made to be Vcc when a similar operation timingfor the data circuits shown in FIGS. 47 and 56 is employed (operationwaveforms shown in FIGS. 48, 53, 54, 57, 48 and 60). Note that theoperation timings of the signals VRFYBA1 and VRFYBB1 are similar tothose in the case where the data circuits shown in FIG. 47 and 56 areemployed.

[0669] Although the seventh embodiment has the structure such that data“2” and “3” are written simultaneously and then data “1” is written, thewriting order is not limited to this and arbitrary writing order may beemployed. For example, an order may be employed in which “1” and “2” arewritten and then “3” is written. Another order may be employed in which“1” and “3” are simultaneously written and then “2” is written.

[0670] (Eighth Embodiment)

[0671] A multilevel storing NAND type EEPROM according to an eighthembodiment of the present invention will now be described.

[0672] Although the seventh embodiment has the structure such thatstates “2” and “3” are substantially written and then state “1” iswritten, the eighth embodiment has the structure such that states “1”,“2” and “3” are substantially simultaneously be written.

[0673] Similarly to the EEPROM according to the seventh embodiment, theEEPROM according to the eighth embodiment has a structure similar tothat according to the sixth embodiment shown in FIGS. 36 and 37.

[0674]FIG. 63 is a circuit diagram showing a data circuit 206F of theEEPROM according to the eighth embodiment of the present invention. Adata circuit 206F shown in FIG. 63 is structured to store four-leveldata.

[0675] As shown in FIG. 63, memory cells M1 to M4 are connected inseries to form a NAND cell. The two ends of the NAND cell respectivelyare connected to the bit line BL and the source line VS through theselection transistors S1 and S2. A memory cell group M sharing thecontrol gate CG forms a unit called a “page” to which data issimultaneously written or from which data is simultaneously read. Amemory cell group connected to the four control gates CG1 to CG4 forms ablock. The page and the block are selected by the control gate/selectiongate driver 202B. Data circuits 206F-0, 2-06F-1, . . . , 206F-m-1 and206F-m are connected to the bit lines BL0 to BLm to temporarily storedata to be written in the corresponding memory cell.

[0676] The relationship between the writing states with respect to thememory cell and the threshold voltages is similar to that according tothe seventh embodiment and is structured, for example, as shown in FIG.46.

[0677] As shown in FIG. 63, write/read data is latched by a flip-flopFF1 formed of n-channel MOS transistors Qn21, Qn22 and Qn23 andp-channel MOS transistors Qp9, Qp10 and Qp11 and a flip-flop FF2 formedof n-channel MOS transistors Qn29, Qn30 and Qn31 and p-channel MOStransistors Qp16, Qp17 and Qp18. The foregoing flip-flops FF1 and FF2serve as sense amplifiers.

[0678] The flip-flops FF1 and FF2 latches whether “0” is written orwhether “1” or “2” or “3” is written as write data information and senseand latch whether the memory cell has information of “0” or informationof “1” or “2” or “3” as data information.

[0679] The data input/output lines I/OA and I/OB and the flip-flop FF1are connected to each other through the n-channel MOS transistors Qn28and Qn27. The data input/output lines I/OC and I/OD and the flip-flopFF2 are connected to each other through the n-channel MOS transistorsQn35 and Qn36. The data input/output lines I/OA, I/OB, I/OC and I/OD areas well as connected to the data input/output buffer 205 shown in FIG.36.

[0680] The gates of the n-channel MOS transistors Qn27, Qn28, Qn35 andQn36 are connected to the output of a column address decoder formed of aNAND logic circuit G2 and an inverter 14. The n-channel MOS transistorsQn26 and Qn34 equalize flip-flops FF1 and FF2 when signals ECH1 and ECH2are “H”. The n-channel MOS transistors Qn24 and Qn32 control theconnection between the flip-flops FF1 and FF2 and a MOS capacitor Qd1.The n-channel MOS transistors Qn25 and Qn33 control the connectionbetween the flip-flops FF1 and FF2 and a MOS capacitor Qd2.

[0681] A circuit formed of the p-channel MOS transistors Qp12C and Qp13Cchanges the gate voltage of the MOS transistor Qd1 in accordance withdata in the flip-flop FF1 when activating signal VRFYBAC has beensupplied. A circuit formed of the p-channel MOS transistor Qp14C andQp15C changes the gate voltage of the MOS capacitor Qd2 in accordancewith data in the flip-flop FF1 and in response to activating signalVRFYBC. A circuit formed of p-channel MOS transistors Qp12C, Qp19C andQp20C changes the gate voltage of the MOS capacitor Qd1 in accordancewith data in the flip-flops FF1 and FF2 and in response to activatingsignal VRFYBA2C. A circuit formed of the p-channel MOS transistor Qp14C,Qp21C and Qp22C changes the gate voltage of the MOS capacitor Qd2 inaccordance with data in the flip-flops FF1 and FF2 and in response toactivating signal VRFYBB2C. A circuit formed of n-channel MOStransistors Qn1C and Qn2C changes the gate voltage of the MOS capacitorQd1 in accordance with data in the flip-flop FF2 and in response toactivating signal VRFYBA1C. A circuit formed of the n-channel MOStransistors Qn3C and Qn4C changes the gate voltage of the MOS capacitorQd2 in accordance with data in the flip-flop FF2 and in response toactivating signal VRFYBB1C.

[0682] Each of the MOS capacitors Qd1 and Qd2 comprises a depletionn-channel MOS transistor and has a capacity which is sufficientlysmaller than the capacity of the bit line. The n-channel MOS transistorQn37 electrically charges the MOS capacitor Qd1 to voltage VA inresponse to signal PREA. The n-channel MOS transistor Qn38 electricallycharges the MOS capacitor Qd2 to voltage VB in response to signal PREB.The n-channel MOS transistors Qn39 and Qn40 control the connectionbetween the data circuit 206F and the bit lines BLa and BLb. A circuitformed of the n-channel MOS transistors Qn37 and Qn38 also serves a bitline voltage controller.

[0683] The operation of the EEPROM having the above-mentioned structurewill now be described with reference to an operation waveform.

[0684] Reading Operation

[0685]FIG. 64 is an operation waveform showing a reading operation.

[0686] As shown in FIG. 64, voltages VA and VB respectively are made tobe 1.8V and 1.5V so that the bit lines BLa and BLb respectively are madeto be 1.8V and 1.5V. Signals BLCA and BLCB are made to be “L” at timet_(1RC) so that the bit line Bla and the MOS capacitor Qd1 are separatedfrom each other and the bit line BLb and the MOS capacitor Qd2 areseparated from each other so that the bit lines BLa and BLb are broughtto a floating state. When the signals PREA and PREB are made to be “L”,the nodes N1 and N2 which are the gate electrodes of the MOS capacitorsQd1 and Qd2 are brought to a floating state.

[0687] At time t_(2RC), the selected control gate CG2A in a blockselected by the control gate/selection gate driver 202B is made to be0V, and the non-selected control gates CG1A, CG3A and CG4A and theselection gates SG1A and SG2A are made to be Vcc. If the thresholdvoltage of the selected memory cell is 0V or lower, the bit line voltageis made to be lower than 1.5V. If the threshold voltage of the selectedmemory cell is 0V or higher, the bit line voltage is maintained at 1.8V.

[0688] Then, at time t_(3RC), the signals BLCA and BLCB are made to be“H” so that data in the bit line is transferred to the MOS capacitorsQd1 and Qd2. Then, the signals BLCA and BLCB are again made to be “L” sothat the bit line Bla and the MOS capacitor Qd1 are separated from eachother and the bit line BLb and the MOS capacitor Qd2 are separated fromeach other. When the signals SAN1 and SAP1 respectively are made to be“L” and “H” so that the flip-flop FF1 is deactivated. When the signalECH1 is made to be “H” so as to be equalized. Then, the signal RV1A andRV1B are made to be “H”.

[0689] At time t_(4RC), the signals SAN1 and SAP1 respectively are againmade to be “H” and “L” so that the voltages of the node N1 is sensed andlatched. As a result, data in the memory cell is sensed whether it is“0” or whether it is “1” or “2” or “3” by the flip-flop FF1 andinformation of this is latched. Then, the selected control gate is madeto be 1V. If the threshold voltage of the selected memory cell is 1V orlower, the bit line voltage is made to be lower than 1.5V. If thethreshold voltage of the selected memory cell is 1V or higher, the bitline voltage is maintained at 1.8V.

[0690] At time t_(5RC), the signals PREA and PREB are made to be “H” sothat the nodes N1 and N2 which are gate electrodes of the MOS capacitorsQd1 and Qd2 respectively are made to be 1.8V and 1.5V. When the signalsPREA and PREB are made to be “L”, the nodes N1 and N2 which are gateelectrodes of the MOS capacitors Qd1 and Qd2 are brought to a floatingstate.

[0691] Then, at time t_(6RC), signals BLCA and BLCB are made to be “H”.The signals BLCA and BLCB are again made to be “L” so that the bit lineBla and the MOS capacitor Qd1 are separated from each other and the bitline BLb and the MOS capacitor Qd2 are separated from each other. Whenthe signals SAN2 and SAP2 respectively are brought to “L” and “H”, theflip-flop FF2 is deactivated and signal ECH2 is made to be “H” so as tobe equalized. Then, the signal RV2A and RV2B are made to be “H”. At timet_(7RC), the signals SAN2 and SAP2 respectively are made to be “H” and“L” so that the voltage of the node N1 is sensed and latched. Thus,whether or not data in the memory cell is “0” or “1” or whether or notdata in the memory cell is “2” or “3” is sensed by the flip-flop FF2 andinformation of this is latched.

[0692]FIG. 65 is a table showing read data sensed and latched by theflip-flops FF1 and FF2 at time t_(7Rc). The potentials of the nodes N3Cand N5C of the flip-flops FF1 and FF2 are as shown in FIG. 65.

[0693] Whether data written in the memory cell is “2” or “3” is sensed.The selected control gate is made to be 2V. If the threshold voltage ofthe selected memory cell is 2V or lower, the bit line voltage is made tobe lower than 1.5V. If the threshold voltage of the selected memory cellis 2V or higher, the bit line voltage of 1.8V is maintained.

[0694] At time t_(8RC), the signals PREA and PREB are made to be “H” sothat the nodes N1 and N2 which are gate electrodes of the MOS capacitorsQd1 and Qd2 respectively are made to be 1.8V and 1.5V. When the signalsPREA and PREB are made to be “L”, the nodes N1 and N2 which are gateelectrodes of the MOS capacitors Qd1 and Qd2 are brought to a floatingstate.

[0695] At time t_(10RC), the signals BLCA and BLCB are made to be “H”.Then, the signals BLCA and BLCB are again made to be “L” so that the bitline Bla and the MOS capacitor Qd1 are separated from each other and thebit line BLb and the MOS capacitor Qd2 are separated from each other.

[0696] Prior to sensing data in the MOS capacitor, VRFYBA2C is made tobe 0V at time t_(11RC). As can be understood from FIG. 65, the node N5Cis made to be “H” and the node N3C is made to be “H” (that is, the nodeN4C is made to be “L”) only when data is “1”. Therefore, only when datais “1”, the p-channel MOS transistors Qp12C, Qp19C and QP20C are turnedon and the node N1 is made to be Vcc. Then, the signals SAN1 and SAP1respectively are made to be “L” and “H” so that the flip-flop FF1 isdeactivated and the signal ECH1 is made to be “H” so as to be equalized.Then, the signals RV1A and RV1B are made to be “H”.

[0697] At time t_(12RC), signals SAN1 and SAP1 are again andrespectively made to be “H” and “L” so that the voltage of the node N1is sensed and latched. Thus, whether data in the memory cell is “2” or“3” is sensed by the flip-flop FF1 and information of this is latched.

[0698]FIG. 66 is a table showing data which is sensed and latched by theflip-flops FF1 and FF2.

[0699] As a result of the foregoing reading operation, four-level datais latched by the flip-flops FF1 and FF2, as shown in FIG. 66. Thethreshold voltages are distributed in FIG. 66 as follows:

[0700] data “0”: threshold voltage is 0V or lower data “1”: thresholdvoltage is 0.5V or higher and 0.8V or lower

[0701] data “2”: threshold voltage is 1.5V or higher and 1.8V or lower

[0702] data “3”: threshold voltage is 2.5V or higher and 2.8V or lower

[0703] During the reading operation, signals VRFYBAC, VRFYBBC, VRFYBA1Cand VRFYBB1C are “L” levels. The voltage VS is 0V.

[0704] When the column activating signal CENB to be supplied to thecolumn address decoder is made to be “H” data stored in the data circuitselected in response to the address signal is output to the datainput/output lines I/OA, I/OB, I/OC and I/OD so as to be output to theoutside of the EEPROM through the data input/output buffer 4.

[0705] The relationship among data stored in the memory cell, thethreshold voltage and levels to be output to the data input/output linesI/OA, I/OB, I/OC and I/OD after data has been read is as shown in FIG.66.

[0706] Data to be output to the outside of the chip may be data obtainedby converting signals output to the data input/output lines I/OA, I/OB,I/OC and I/OD by the data input/output buffer 5.

[0707] Writing Operation

[0708] Initially, write data is loaded into the flip-flops FF1 and FF2.Then, data “1”, “2” and “3” are substantially simultaneously written.Verify read is performed to detect whether or not data “1”, “2” and “3”have been sufficiently written. If memory cell to which data has notbeen sufficiently written exists, writing is again performed. When thewrite completion detecting circuit has detected that data has beensufficiently written in all of the memory cells, the writing operationis completed.

[0709] A program will now be described, followed by describing verifyread.

[0710] Program

[0711] Prior to performing the writing operation, supplied data for twobits is converted by the data input/output buffer 205 so as to besupplied to the data circuit 206F.

[0712]FIG. 67 is a table showing write data to be supplied to the datacircuit 206F and latched by the flip-flops FF1 and FF2. The relationshipbetween the four-level data and the data input/output lines I/OA, I/OB,I/OC and I/OD is as shown in FIG. 67.

[0713] Converted four-level data is transferred to a data circuit at acolumn address instructed with the address signal when the columnactivating signal CENB is “H”.

[0714]FIG. 68 is an operation waveform showing the writing operation.

[0715] At time t_(1s), voltage VA is made to be the bit line writingcontrol voltage 1V so that the bit line BLa is made to be 1V. Whenvoltage drop of the n-channel MOS transistor Qn39 corresponding to thethreshold voltage raises a problem, the level of the signal BLCA isrequired to be raised. Then, the signal PRE is made to be “L” so thatthe bit line is brought to a floating state.

[0716] At time t_(2s), the signal RV2A is made to be 1.5V. As a result,bit line control voltage of 0V is applied to the bit line of the columnshaving data “1” or “3”. When the threshold voltage of the n-channel MOStransistor Qn32 is made to be 1V, the n-channel MOS transistor Qn32 isturned off when “0” or “2” is written. When “1” or “3” is written, then-channel MOS transistor Qn32 is turned on.

[0717] At time t_(3s), VRFYBAC is made to be 0V, and bit line writecontrol voltage Vcc is, to the bit line, output from the data circuitstoring data “0” or data “1”.

[0718] Then, VRFYBA2C is made to be 0V at time t_(4s), and biasing toVRFYBA1 from the data circuit storing data “1” is performed andpotential of 2V for writing “1” on the bit line is output to the bitline.

[0719] As a result, the bit line for writing “0” is made to be Vcc, thebit line for writing “1” is made to be 2V, the bit line for writing “2”is made to be 1V and the bit line for writing “3” is made to be 0V.

[0720] At timet_(l , selection gate SG1A and control gates CG1A to CG4A of the block selected by the election gate/selection gate driver 202B are made to be Vcc. The selection gate SG2A is made to be)0V.

[0721] Then, the selected control gate CG2A is made to be high voltageof VPP (for example, 20V), while the non-selected control gates CG1A,CG3A and CG4A are made to VM (for example, 10V). In the memory cellcorresponding to a data circuit storing data “3”, the difference in thepotential between the channel potential of 0V and VPP of the controlgate causes electrons to be injected into the floating gate so that thethreshold voltage is increased. In the memory cell corresponding to thedata circuit storing data “2”, the difference in the potential betweenthe channel potential of 1V and VPP of the control gate causes electronsto be injected into the floating gate so that the threshold voltage isincreased. In the memory cell storing data “1”, the difference in thepotential between the channel potential of 2V and VPP of the controlgate causes electrons to be injected into the floating gate so that thethreshold voltage is increased. The reason why the channel potential ismade to be 1V when “2” is written and the same is made to be 2V when “1”is written is that the quantity of electrons is reduced in thesequential order as the case in which data “3” is written, the case inwhich data “2” is written and the case in which data “1” is written. Inthe memory cell corresponding to the data circuit storing data “0”, thedifference in the potential between the channel potential and VPP of thecontrol gate is small. Therefore, substantially no electrons is injectedinto the floating gate. Therefore, the threshold voltage of the memorycell is not changed. During the writing operation, signals SAN1, SAN2,PREB and BLCB are “H” level, signals SAP1, SAP2, VRFYBA1C, RV1A, RV1B,RV2B, ECH1 and ECH2 are “L” level and the voltage VB is 0V.

[0722] (2) Verify Read

[0723] After the writing operation has been completed, whether or notwriting has been performed sufficiently is detected (write verify). If arequired threshold voltage has been realized, data in the data circuitis changed to “0”. If a required threshold voltage has not beenrealized, data in the data circuit is maintained and writing is againperformed. The writing operation and the write verify are repeated untilthe memory cell for writing “1”, that for writing “2” and that forwriting “3” reach required threshold voltages.

[0724]FIGS. 69 and 70 are operation waveforms showing the verify readoperation. FIG. 70 shows timings following the timings shown in FIG. 69.

[0725] Referring to FIGS. 69 and 70, the write verify operation will nowbe described.

[0726] Initially, it is determined whether or not the memory cell forwriting “1” has reached a predetermined threshold voltage.

[0727] As shown in FIG. 69, at time t_(1yc), voltage VA and VBrespectively are made to be 1.8V and 1.5V so that bit lines BLa and BLbrespectively are made to be 1.8V and 1.5V. When signals BLCA and BLCBare made to be “L” and the bit line BLa and the MOS capacitor Qd1 areseparated from each other and the bit line BLb and the MOS capacitor Qd2are separated from each other. Moreover, the bit line BLa and BLb arebrought to a floating state. When the signals PREA and PREB are made tobe “L”, the nodes N1 and N2 which are the gate electrodes of the MOScapacitors Qd1 and Qd2 are brought to a floating state.

[0728] At time t_(2yc), the selected control gate CG2A in a blockselected by the control gate/selection gate driver 202B is made to be0.5V, and the non-selected control gates CG1A, CG3A and CG4A and theselection gates SG1A and SG2A are made to be Vcc. If the thresholdvoltage of the selected memory cell is 0.5V or lower, the bit linevoltage is made to be lower than 1.5V. If the threshold voltage of theselected memory cell is 0.5V or higher, the bit line voltage ismaintained at 1.8V.

[0729] Then, at time t_(3yc), the signals BLCA and BLCB are made to be“H” so that the potential of the bit line is transferred to the nodes N1and N2. Then, the signals BLCA and BLCB are made to be “L” so that thebit line Bla and the MOS capacitor Qd1 are separated from each other andthe bit line BLb and the MOS capacitor Qd2 are separated from eachother. At time t_(4yc), RV1a is made to be 1.5V. When data “2” iswritten or when data “3” is written, node N1 is electrically dischargedto 0V.

[0730] At time t_(5yc), the signal VRFYBA1C is made to be “H” so thatthe n-channel MOS transistor Qn2 of the data circuit storing write data“0” or “2” is turned on and node N1 is made to be Vcc. As a result, thenode N1 is made to be Vcc when data “0” is written or when data “2” iswritten When data “3” is written, the node N1 is made to be 0V.

[0731] The signals SAN2 and SAP2 respectively are made to be “L” and “H”so that the flip-flop FF2 is deactivated and the signal ECH2 is made tobe “H” so as to be equalized. Then, the signals RV2A and RV2B are madeto be “H”. When the signals SAN2 and SAP2 are again and respectivelymade to be “H” and “L”, the voltage of the node N1 is sensed and latchedat time t_(6yc). Thus, it is determined whether or not data in thememory cell corresponding to only the data circuit storing write data“1” has been sufficiently brought to the state for writing data “1”. Ifdata in the memory cell is “1”, the voltage of the node N1 is sensed andlatched by the flip-flop FF2 so that write data is changed to “0”. Ifdata in the memory cell is not “1”, the flip-flop FF1 senses and latchesthe voltage of the node N2 to maintain the write data to be “1”. Data tobe written in the data circuit storing “0” or “2” or “3” is not changed.

[0732] Then, the selected control gate is made to be 1.5V. If thethreshold voltage of the selected memory cell is 1.5V or lower, the bitline voltage is made to be lower than 1.5V. If the threshold voltage ofthe selected memory cell is 1.5V or higher, the bit line voltage ismaintained at 1.8V. At time t_(7yc), signals PREA and PREB are made tobe Vcc so that the nodes N1 and N2 are made to be 1.8V and 1.5V. Then,the nodes N1 and N2 are brought to the floating gate state.

[0733] At time t_(8yc), the signals BLCA and BLCB are made to be “H” sothat the potential of the bit line is transferred to the nodes N1 andN2. Then, the signals BLCA and BLCB are made to be “L” so that the bitline Bla and the bit line BLb and the MOS capacitor Qd2 are separatedfrom each other.

[0734] At time t_(9yc), the signal RV2A is made to be voltage not higherthan Vcc, for example, 1.5V. If the threshold voltage of the n-channelMOS transistor Qn32 is 1V , the n-channel MOS transistor Qn32 of thedata circuit storing write data “3” is turned on and the node N1 is madeto be 0V. In a case where the threshold voltage of the n-channel MOStransistor Qn32 is 1V, the n-channel MOS transistor Qn32 of the datacircuit storing write data “3” is turned on and the node N1 is made tobe 0V. If data “2” has been sufficiently written in the memory cell ofthe data circuit storing write data of “2”, the n-channel MOS transistorQn32 is turned off so that the node N1 is maintained at 1.5V or higher.If data “2” has not been sufficiently written, the node N1 is 1.5V orlower.

[0735] When the VRFYBAC is made to be “L” at time t_(10yc), thep-channel MOS transistor Qp13 of the data circuit storing write data “0”or “1” is turned on so that the node N1 is made to be Vcc.

[0736] The signals SAN1 and SAP1 respectively are made to be “L” and “H”so that the flip-flop FF1 is deactivated and the signal ECH1 is made tobe “H” so as to be equalized. Then, the signals RV1A and RV1B are madeto be “H”. When the signals SAN1 and SAP1 respectively are again made tobe “H” and “L”, the voltage of the node N1 is sensed and latched at timet_(11yc). Whether or not data in the memory cell corresponding to onlythe data circuit storing write data “2” has been sufficiently brought tothe state for writing “2” is detected. If data in the memory cell is“2”, the voltage of the node N1 is sensed and latched by the flip-flopFF1 so that write data is changed to “0”. If data in the memory cell isnot “2”, the voltage of the node N1 is sensed and latched by theflip-flop FF1 so that write data “2” is maintained. Write data in thedata circuit storing write data “0” or “1” or “3” is not changed.

[0737] Then, the selected control gate is made to be 2.5V. If thethreshold voltage of the selected memory cell is 2.5V or lower, the bitline voltage is made to be lower that 1.5V. If the threshold voltage ofthe selected memory cell is 2.5V or higher, the bit line voltage ismaintained at 1.8V. At time t_(12yc), signals BLCA and BLCB are made tobe “H” so that the potential of the bit line is transferred to the nodesN1 and N2. When the signals BLCA and BLCB are again made to be “L”, thebit line Bla and the MOS capacitor Qd1 are separated from each other andthe bit line BLb and the MOS capacitor Qd2 are separated from eachother.

[0738] At time t_(13yc), the VRFYBAC is made to be “L” so that thep-channel MOS transistor Qp13c of the data circuit storing write data“0” or “1” or the data circuit on which “2” has been sufficientlywritten is turned on so that the node N1 is made to be Vcc. When thesignals SAN1 and SAP1 respectively are made to be “L” and “H” so thatthe flip-flop FF1 is deactivated and the signal ECH1 is made to be “H”and equalized. Then, the signals RV1A and RV1B are made to be “H”. Attime t_(14yc), the signals SAN1 and SAP1 respectively are made to be “H”and “L” so that the voltage of the node N1 is sensed and latched.

[0739] Then, write data is changed, as shown in FIG. 70. At timet_(15yc), signals BLCA and BLCB are made to be “H” so that the portionof the bit line is transferred to the nodes N1 and N2. The signals BLCAand BLCB are again made to be “L” so that the bit line Bla and the MOScapacitor Qd1 are separated from each other and the bit line BLb and theMOS capacitor Qd2 are separated from each other. At time t_(16yc), theVRFYBA1C is made to be “H” so that the n-channel MOS transistor Qn2C ofthe data circuit storing write data “0” or “2” and the data circuit onwhich “1” has been sufficiently written is turned on so that the node N1is made to be Vcc. The signals SAN2 and SAP2 respectively are made to be“L” and “H” so that the flip-flop FF2 is deactivated and the signal ECH2is made to be “H” and equalized. Then, the signal RV2A and RV2B are madeto be “H”. At time t_(17yc), the signals SAN2 and SAP2 respectively aremade to be, “H” and “L” so that the voltage of the node N1 is sensed andlatched.

[0740] In the above-mentioned embodiment, the VRFYBA1C is made to be Vccat time t_(16yc) to electrically charge the node N1 of the MOS capacitorQd1 to be higher than the potential (1.5V) of the node N2 when “0” iswritten and when “2” is written. A structure may be employed in whichRV2B is made to be, for example, 1.5V at time t_(16yc). In this case,“0” or “2” is written, the n-channel MOS transistor Qn33 is turned onbecause the node N6C is 0V. Therefore, the node N2 is made to be 0V. If“1” or “3” is written, the n-channel MOS transistor Qn33 is turned offbecause the node N6C is Vcc and the node N2 is 1.5V so that the node N2maintains 1.5V. At time t_(16yc), VRFYBA1C is made to be Vcc to performthe foregoing operation. Since the level to which the node N1 must beelectrically charged when “0” is written or “2” is written is requiredto be higher than the potential (0V) of the node N2, the node N1 isrequired to be electrically charged to a low level of, for example,about 0.5V.

[0741] As described above, data in the memory cell corresponding to onlythe data circuit storing write data of “3” has been sufficiently broughtto the state for writing “3” is detected. If data in the memory cell is“3”, the flip-flops FF1 and FF2 sense and latch the voltage of the nodeN1 so that write data is changed to “0”. If data in the memory cell isnot “3”, the flip-flops FF1 and FF2 sense and latch the voltage of thenode N1 so that the write data of “3” is maintained. Write data in thedata circuit storing write data “0” or “1” or “2” is not changed.

[0742] During the write verify, the signal VRFYBBC is made to be “H”,the signal VRFYBB1C is made to be “L” and the voltage VS is made to be0V.

[0743] If all of the selected memory cells have reached requiredthreshold voltages, data in the data circuit is made to be “0”. That is,when writing has been completed, the nodes N4C and N6C are made to be“L”. By detecting this, it can be determined whether or not all of theselected memory cell have reached required threshold voltages.

[0744] After writing and verify read have been completed, writecompletion simultaneous detection is performed to determine whether ornot data has been written in all of the columns.

[0745]FIG. 63 is a circuit diagram showing a data circuit 206F havingthe write completion simultaneous detection transistor.

[0746] Completion of writing can be detected by using a write completionsimultaneous detection transistors Qn5C and Qn6C formed as shown in FIG.63. After verify read has been performed, VRTC is precharged to, forexample, Vcc. If one or more memory cell in which data has been writteninsufficiently exists, at least either the node N4C or the node N6C ofthe data circuit is “H”. Therefore, at least either the n-channel MOStransistor Qn5C or the n-channel MOS transistor Qn6C is turned on sothat the level of VRTC is lowered from the precharge level. When datahas been sufficiently written on all of the memory cells, the nodes N4Cand N6C of the data circuits 206F-0, 206F-1, . . . , 206F-m-1 are madeto be “L”. As a result, the N-channel MOS transistors Qn5C and Qn6C inall of the data circuits are turned off so that VRTC holds theprecharged potential.

[0747] The EEPROM according to the eighth embodiment has theabove-mentioned structure. The verify read, writing and usual readingoperations are not limited to the foregoing descriptions. Otheroperations may be employed.

[0748]FIG. 71 is an operation waveform showing another verify readoperation.

[0749] The verify read first cycle may be structured, for example, asshown in the operation waveform shown in FIG. 71.

[0750] In the verify read first cycle shown in FIG. 71, the operation totime t_(12yc) is the same as the verify read first cycle shown in FIG.70. The operation is different from the same from time t_(12yc).

[0751] At time t_(12yc), the signals BLCA and BLCB are made to be “H”,and the potential of the bit line is transferred to the nodes N1 and N2.If the threshold voltage of the memory cell is 2.5V or higher, the bitline Bla is 1.5V or higher. If the threshold voltage of the memory cellis 2.5V or lower, the bit line BLb is 1.5V or lower. Then, the signalsBLCA and BLCB are made to be “L” so that the bit line Bla and the MOScapacitor Qd1 are separated from each other and the bit line BLb and theMOS capacitor Qd2 are separated from each other.

[0752] When the signal VRFYBA1C has been made to be “H” at timet_(13zc), the n-channel MOS transistor Qn2 of the data circuit storingwrite data “0” or “2” and the data circuit on which “1” has beensufficiently written is turned on. Therefore, the node N1 is made to be1.5V or higher. When the signals SAN2 and SAP2 have respectively beenmade to be “L” and “H”, the flip-flop FF2 is deactivated so that thesignal ECH2 is made to be “H” and equalized. Then, the signals RV2A andRV2B are made to be “H”. At time t_(14zc), the signals SAN2 and SAP2respectively are made to be “H” and “L” so that the voltage of the nodeN1 is sensed and latched.

[0753] Then, write data is changed, as shown in FIG. 71. At timet_(15zc), the signals BLCA and BLCB are made to be “H” so that thepotential of the bit line is transferred to the nodes N1 and N2. Then,the signals BLCA and BLCB are again made to be “L” so that the bit lineBla and the MOS capacitor Qd1 are separated from each other and the bitline BLb and the MOS capacitor Qd2 are separated from each other.

[0754] When the signal VRFYBAC has been made to be “L” at time t_(16zc),the p-channel MOS transistor Qp13 of the data circuit storing write data“0” or “1” and the data circuit on which data “2” has been sufficientlywritten is turned on and the node N1 is made to be Vcc. The signals SAN1and SAP1 respectively are made to be “L” and “H” so that the flip-flopFF1 is deactivated, and the signal ECH1 is made to be “H” and equalized.Then, the signal RV1A and RV1B are made to be “H”. When the signals SAN1and SAP1 respectively are made to be “H” and “L” at time t_(17zc), thevoltage of the node N1 is sensed and latched.

[0755] Also the circuit of the data circuit according to the eighthembodiment is not limited to that shown in FIG. 63. Therefore, anothercircuit structure may be employed.

[0756]FIGS. 72, 73, 74 and 75 are circuit diagrams showing otherstructures.

[0757] The operation timing of the signals VRFYBA1C and VRFYBB1C for thedata circuit 206G shown in FIG. 72 may be determined such that Vcc ismade to be 0V and 0V is made to be Vcc when a similar operation timingfor the data circuits shown in FIG. 63 is employed (operation waveformsshown in FIGS. 65, 68, 69, 70 and 71). Note that the operation timingsof the signals VRFYBAC, VRFYBBC, VRFYBA2C and VRFYBB2C are similar tothose in the case where the data circuit 206F shown in FIG. 63 isemployed.

[0758] The operation timing of the signals VRFYBAC, VRFYBBC, VRFYBA2Cand VRFYBB2C for the data circuit 206H shown in FIG. 73 may bedetermined such that Vcc is made to be 0V and 0V is made to be Vcc whena similar operation timing for the data circuit 206F shown in FIG. 63 isemployed (operation waveforms shown in FIGS. 65, 68, 69, 70 and 71).Note that the operation timings of the signals VRFYBA1C and VRFYBB1C aresimilar to those in the case where the data circuit 206F shown in FIG.63 is employed.

[0759] The operation timing of the signals VRFYBAC and VRFYBBC for thedata circuit 206I shown in FIG. 74 may be determined such that Vcc ismade to be 0V and 0V is made to be Vcc when a similar operation timingfor the data circuit 206F shown in FIG. 63 is employed (operationwaveforms shown in FIGS. 65, 68, 69, 70 and 71). Note that the operationtimings of the signals VRFYBA1C, VRFYBB1C, VRFYBA2C and VRFYBB2C aresimilar to those in the case where the data circuit 206F shown in FIG.63 is employed.

[0760] The operation timing of the signals VRFYBA2C and VRFYBB2C for thedata circuit 206J shown in FIG. 75 may be determined such that Vcc ismade to be 0V and 0V is made to be Vcc when a similar operation timingfor the data circuit 206F shown in FIG. 63 is employed (operationwaveforms shown in FIGS. 65, 68, 69, 70 and 71). Note that the operationtimings of the signals VRFYBA2C, VRFYBB2C, VRFYBAC1C and VRFYBB1C aremade to be Vcc, they may be made to be Vcc+Vth (Vth is the thresholdvoltage of the n-channel MOS transistor) or Vcc+2Vth. In this case, then-channel MOS transistor is able to transfer the potential withoutlowering of the threshold voltage.

[0761] The eighth embodiment has the structure such that the bit line isprecharged when the reading operation is performed or when the verifyread is performed, and then the non-selected control gates CG1A, CG3Aand CG4A are made to be Vcc to turn in the memory cells having the CG1A,CG3A and CG4A as the gate electrodes.

[0762] A structure may be employed in which the non-selected controlgates CG1A, CG3A and CG4A are made to be Vcc and then brought to thefloating state followed by precharging the bit line. Another structuremay be employed in which the bit line is precharged and then thenon-selected control gate is made to be Vcc followed by bringing thenon-selected control gate to the floating state. In this case, thenon-selected control gate is in the floating state in a period in whichthe electric current flows from the bit line to the source line. In theperiod in which the read current flows, the channel of the memory cellhaving the non-selected control gate as the gate electrode is increasedfrom 0V. As a result, capacity coupling between the channel and thenon-selected control gate causes the potential of the non-selectedcontrol gate to be higher than Vcc. When the potential of thenon-selected control gate is higher than Vcc, the resistance of thememory cell having the non-selected control gate as the gate electrodeis reduced. As a result, the read electric current is raised and thusreading speed can be raised.

[0763] (Ninth Embodiment)

[0764] A multilevel storing NAND type EEPROM according to a ninthembodiment of the present invention will now be described.

[0765] Similarly to the EEPROM according to the eighth embodiment, theEEPROM according to the ninth embodiment has a similar structure to thestructure according to the sixth embodiment shown in FIGS. 36 and 37.

[0766]FIG. 76 is a circuit diagram showing a data circuit 206K of theEEPROM according to the ninth embodiment of the present invention. Thedata circuit 206K shown in FIG. 76 is structured to store four-leveldata.

[0767] The data circuit 206K shown in FIG. 76 includes two latches (afirst latch FF1 and a second latch FF2). When writing is performed,two-bit write data is stored in the two latches. When reading isperformed, read four-level data is stored in the two latches, and thenoutput to the outside of the chip through I/OA to I/OD.

[0768] As shown in FIG. 76, write/read data is latched by a flip-flopFF1 formed of n-channel MOS transistors Qn21, Qn22 and Qn23 andp-channel MOS transistors Qp9, Qp10 and Qp11 and a flip-flop FF2 formedof n-channel MOS transistors Qn29, Qn30 and Qn31 and p-channel MOStransistors Qp16, Qp17 and Qp18. The foregoing flip-flops FF1 and FF2serve as sense amplifiers.

[0769] The flip-flops FF1 and FF2 latch whether “0” or “1” or “2” or “3”is written as write data information and sense and latch whether thememory cell has information of “0” or “1” or “2” or “3” as datainformation.

[0770] The data input/output lines I/OA and I/OB and the flip-flop FF1are connected to each other through the n-channel MOS transistors Qn28and Qn27. The data input/output lines I/OC and I/OD and the flip-flopFF2 are connected to each other through the n-channel MOS transistorsQn35 and Qn36. The data input/output lines I/OA, I/OB, I/OC and I/OD areas well as connected to the data input/output buffer 205 shown in FIG.36. The gates of the n-channel MOS transistors Qn27 and Qn28, areconnected to the output of a column address decoder formed of a NANDlogic circuit G2 and an inverter I4.

[0771] The n-channel MOS transistors Qn26 and Qn34 equalize flip-flopsFF1 and FF2 when signals ECH1 and ECH2 are “H”. The n-channel MOStransistors Qn24 and Qn32 control the connection between the flip-flopsFF1 and FF2 and a MOS capacitor Qd1. The n-channel MOS transistors Qn25and Qn33 control the connection between the flip-flops FF1 and FF2 and aMOS capacitor Qd2.

[0772] A circuit formed of the p-channel MOS transistors Qn50C and Qn51Cchanges the gate voltage of the MOS transistor Qd1 in accordance withdata in the flip-flop FF1 and in response to activating signal VRFYBAC.A circuit formed of the p-channel MOS transistor Qn52C and Qn53D changesthe gate voltage of the MOS capacitor Qd2 in accordance with data in theflip-flop FF1 and in response to activating signal VRFYBBC. A circuitformed of the n-channel MOS transistors Qn53C, Qn54C and Qn55C changesthe gate voltage of the MOS capacitor Qd1 in accordance with data in theflip-flops FF1 and FF2 and in response to activating signal RRFYBA2C. Acircuit formed of the n-channel MOS transistors Qn56C, Qn57C and Qn58Cchanges the gate voltage of the MOS capacitor Qd2 in accordance withdata in the flip-flops FF1 and FF2 and in response to activating signalVRFYBB2C. A circuit composed on the n-channel MOS transistors Qn1C andQn2C changes the gate voltage of the MOS capacitor Qd1 in accordancewith data in the flip-flop FF2 and in response to activating signalVRFYBA1C. A circuit formed of the n-channel MOS transistors Qn3C andQn4C changes the gate voltage of the MOS capacitor Qd2 in accordancewith data in the flip-flop FF2 and in response to activating signalVRFYBB1C.

[0773] Each of the MOS capacitors Qd1 and Qd2 comprises depletionn-channel MOS transistors and have capacities which are sufficientlysmaller than the capacity of the bit line. The n-channel MOS transistorQn37 electrically charges the MOS capacitor Qd1 to voltage VA inresponse to signal PREA. The n-channel MOS transistor Qn38 electricallycharges the MOS capacitor Qd2 to voltage VB in response to signal PREB.The n-channel MOS transistors Qn39 and Qn40 control the connectionbetween the data circuit 3 and the bit lines Bla and Blb in response tosignals BLCA and BLCB. A circuit formed of the n-channel MOS transistorsQn37 and Qn38 also serves as a bit line voltage controller.

[0774] The operation of the EEPROM having the above-mentioned structurewill now be described with reference to the operation waveform. In thefollowing description, a state where control gate CG2A has been selectedwill now be described.

[0775] Reading Operation

[0776]FIG. 77 is an operation waveform showing a reading operation.

[0777] As shown in FIG. 77, at time t_(w1), voltages VA and VBrespectively are made to be 1.8V and 1.5V so that the bit lines BLa andBLb respectively are made to be 1.8V and 1.5V. The signals PREA and PREBare made to be “L” so that the bit lines BLa and BLb are brought to thefloating state.

[0778] At time t_(w2), the selected control gate CG2A in the blockselected by the control gate/selection gate driver 202B is made to be1V, non-selected control gates CG1A, CG3A and CG4A and selection gatesSG1A and SG2A are made to be Vcc. If the threshold voltage of theselected memory cell is 1V or lower, the bit line voltage is lower than1.5V. If the threshold voltage of the selected memory cell is 1V orhigher, the bit line voltage of 1.8V is maintained. Then, the signalsSAN1 and SAP1 respectively are made to be “L” and “H” so that theflip-flop FF1 is deactivated and the signal ECH1 is made to be “H” andequalized.

[0779] At time t_(3w), the signal RV1A and RV1B are made to be “H”. Attime tw4, the signals SAN1 and SAP1 are again made to be “H” and “L” sothat the voltage of the node N1 is sensed and latched. As a result, itis determined whether data in the memory cell is “0 or 1” or “2 or 3” issensed by the flip-flop FF1 and information of this is latched.

[0780] Then, it is determined whether the threshold voltage of thememory cell is 0V or higher; or 0V or lower. At time t_(w5), the bitline Bla and the dummy bit line BLb respectively are precharged to 1.8Vand 1.5V followed by brining the bit line Bla and the dummy bit line BLbto the floating state.

[0781] At time t_(w6), the selected control gate is made to be 0V. Ifthe threshold voltage of the selected memory cell is 0V or lower, thebit line voltage is lower than 1.5V. If the threshold voltage of theselected memory cell is0V or higher, the bit line voltage of 1.8V ismaintained. The signals SAN2 and SAP2 respectively are made to be “L”and “H” so that the flip-flop FF2 is deactivated and signal ECH2 is madeto be “H” and equalized. At time t_(w7), the signals RV2A and RV2B aremade to be “H”.

[0782] At time t_(w8), the signals SAN2 and SAP2 respectively are madeto be “H” and “L” so that the voltage of the node N1 is sensed andlatched. Thus, it is determined whether data in the memory cell is “0”or “1 or 2 or 3” is sensed by the flip-flop FF2 and information of thisis latched.

[0783]FIG. 78 is a table showing read data sensed and latched by theflip-flops FF1 and FF2 at time t_(w8). The potentials of the nodes N3Cand N5C of the flip-flops FF1 and FF2 are as shown in FIG. 78.

[0784] Finally, whether data written in the memory cell is “0 or 1 or 2”or “3” is sensed. At time t_(w9), the bit line Bla and the dummy bitline BLb are precharged to 1.8V and 1.5V , respectively. Then, the bitline Bla and the dummy bit line BLb are brought to the floating state.Then, the selected control gate is made to be 2V at time t_(w10). If thethreshold voltage of the selected memory cell is 2V or lower, the bitline voltage is lower than 1.5V. If the threshold voltage of theselected memory cell is 2V or higher, the bit line voltage of 1.8V ismaintained. At time t_(w11), VRFYBA2C is made to be Vcc.

[0785] As can be understood from FIG. 78, the node N5C is made to be “H”and the node N3C is made to be “L” (that is, the node N4C is made to be“H” ) only when data is “1”. Therefore, only when data is “1”, then-channel MOS transistors Qn54C, Qn55C and Qn53C are turned on and thenode N1 is made to be Vcc. Then, the signals SAN2 and SAP2 respectivelyare made to be “L” and “H” so that the flip-flop FF2 is deactivated andthe signal ECH2 is made to be “H” and equalized. At time t_(w12), thesignals RV2A and RV2B are made to be “H”. At time t_(w13), the signalsSAN2 and SAP2 are again made to be “H” and “L” so that the voltage ofthe node N1 is sensed and latched. Thus, whether data in the memory cellis “0 or 1 or 2” or “3” is sensed by the flip-flop FF2 and informationof this is latched.

[0786]FIG. 79 is a table showing read data which is sensed and latchedby the flip-flops FF1 and FF2.

[0787] Two-bit data stored by the flip-flops FF1 and FF2 is output tothe outside of the chip when CENB is activated at time t_(w14).

[0788] The writing operation and write verify read operation are similarto those according to the eighth embodiment.

[0789] In the ninth embodiment, the bit lines and the dummy bit linesare precharged prior to applying a predetermined reading voltages (forexample, 0V, 1V and 2V) to the word lines.

[0790] On the other hand, the eighth embodiment has the structure suchthat the bit line and the dummy bit line are first precharged whenreading and verify reading are performed. Then, no precharge isperformed and the word line reading voltage is changed (for example, itis changed from 0V to 1V and 2V). Also the eighth embodiment having theforegoing structure may be structured such that the bit line and thedummy bit line are precharged similarly to the ninth embodiment wheneverreading voltage (for example, 0V, 1V and 2V) is applied to the word linewhen reading or verify reading is performed.

[0791] Although the sixth to ninth embodiments have the above-mentionedstructures, the sixth to ninth embodiments may be modified as follows:

[0792]FIG. 80 is a diagram showing an EEPROM having a modified columnstructure.

[0793] In the sixth to ninth embodiments, only data circuit 206corresponds to each of right and left bit lines BL. A structure may beemployed in which one data circuit 206L corresponds to each of aplurality of right and left bit lines BL.

[0794] As shown in FIG. 80, the modified EEPROM has a structure suchthat one of data circuits 206L-0 to 206L-m is provided for four bitlines BLai-1 to Blai-4 or BLbi-1 to BLbi-4 (i is any one of 0 to 3).

[0795] A portion including the memory cell array 201-1 will now bedescribed.

[0796] When the bit line BLai-1 is selected from the four bit linesBLai-1 to BLai-4, signal BLC1 of the drive signals BLC1 to BLC4 fordriving the transfer gate circuit 207A-1 in the portion including thebit line controller 203C is made to be “H” level and the other signalsBLC2 to 4 are made to be “L” level. Simultaneously, the signal BLC1D ofthe drive signals BLC1D to BLC4D for driving the transfer gate 207B inthe portion including the non-selected bit line controller 20 is made tobe “L” level and the other signals BLC2D to BLC4D are made to be “H”level. As a result, only the selected bit line BLi-1 is connected to thedata circuits 206L-0 to 206L-m.

[0797] Thus, only the selected bit line BLai-1 is connected to the datacircuits 206L-0 to 206L-m while the non-selected bit lines BLai-2 toBLai-4 are connected to the non-selected bit line controllers 20-0A to20-mA. The non-selected bit line controllers 20-0A to 20-mA control thepotentials of the non-selected bit lines BLai-2 to BLai-4.

[0798] As described above, according to the sixth to ninth embodiments,when data is written, at least one bit line controller electricallycharges the bit line to a required bit line write control voltage. As aresult, a bit line voltage controller can be realized which has a simplestructure and which applies bit line write control voltage correspondingto n-level write data to the bit line. Thus, an n-level storing EEPROMcan be obtained which is able to reduce the size of the column-systemcircuit and the size of the chip and which is suitable to realize ahighly integrated structure.

[0799] Assuming that the number of multilevel data is 2^(m) (m is anatural number not smaller than 2)=n for latching write data into thememory cell and sensing and latching read data from the memory cell, thenumber of the flip-flops can be made to be m. Therefore, the size of thecolumn-system circuit can be reduced. The determination circuit providedfor determining whether or not re-writing is performed duringverification is controlled in accordance with write data which isupdated in the data latch/sense amplifier in accordance with a result ofverify read.

[0800] The number “n” of multilevel data may be a natural numbersatisfying 2^(m−1)<n ≦2^(m).

[0801] (Tenth Embodiment)

[0802]FIG. 81 is a diagram showing the structure of a multilevel storingEEPROM according to a tenth embodiment of the present invention.

[0803] As shown in FIG. 81, a row-system circuit 302 and a column-systemcircuit 303 are provided for a memory cell array 301 having memory cellsarranged in the matrix manner.

[0804] The row-system circuit 302 includes a row decoder 302A forreceiving an address signal output from an address buffer 304 to selecta row of the memory cell array 301 in response to the supplied addresssignal, and a word line driver 302B for driving a word line of thememory cell array 301 in accordance with an output from the row decoder302A. In this embodiment, a NAND type EEPROM will now be described whichcomprises word lines which are selection gates (SG) and control gates(CG). Therefore, the word line driver 302B is sometimes called a controlgate/selection gate driver. The control gate/selection gate driver 302Bselects a selection gate (SG) and a control gate (CG) in response to theaddress signal to apply writing voltage, reading voltage and the like tothe selected selection gate and control gate.

[0805] The column-system circuit 303 includes a column decoder 303A forreceiving the address signal output from the address buffer 304 toselect a column of the memory cell array and a column selection linedriver 303B for driving the column selection line for selecting a columnof the memory cell array 301 in accordance with an output from thecolumn decoder 303A.

[0806] Moreover, the column-system circuit 303 includes a bit linecontroller 303C for temporarily storing data to be written in the memorycell and reading data in the memory cell. The bit line controller 303Cis connected to a data input/output circuit (data input/output buffer)305. The bit line controller 303C receives write data from the datainput/output buffer 305 when data is written to output the receivedwrite data to the memory cell. On the other hand, the bit linecontroller 303C receives data read from the memory cell to outputreceived data to the data input/output buffer 305.

[0807] The data input/output buffer 305 controls input/output of datasuch that it introduces write data supplied from outside of the EEPROMand outputs data read from the memory core portion to the outside of theEEPROM. Moreover, the data input/output buffer 305 has a functionserving as an interface between the outside of the EEPROM and the memorycore portion. For example, the data input/output buffer 305 has afunction for encoding four-level data read from the memory core portioninto two-bit data to output the same to the outside and a function fordecoding two-bit data supplied from the outside of the EEPROM intofour-level data to introduce the same to the memory core portion.

[0808]FIG. 82 is a diagram showing the structure of the memory cellarray 301 and the column-system circuit 303 shown in FIG. 81.

[0809] As shown in FIG. 82, the memory cell array 301 has memory cellsMC arranged in the matrix manner. The EEPROM according to thisembodiment has a structure such that one cell MC includes a plurality ofmemory cell transistors M1 to M4 connected in series so that a NAND cellMC is formed. An end of the cell MC is connected to bit line BL througha selection transistor S1, while another end of the same is connected toa source line VS through a selection transistor S2. A group of thememory cell transistors M sharing the control gate CG forms a unitcalled a “page”. Data is written and read simultaneously in page units.A group of memory cell transistors M connected to four control gates CG1to CG4 forms a unit called a “block”. The page and block respectivelyare selected by control gate/selection gate driver.

[0810] Data circuits 306-0 to 306-m respectively are connected betweenthe bit lines BL0 to BLm and data input/output line I/O. The datacircuits 306-0 to 306-m have a function for temporarily storing data tobe written in the memory cell and a function for sensing and temporarilystoring data read from the memory cell.

[0811]FIG. 83 is a graph showing the threshold voltage of the memorycell transistor M and four writing states (four-level data “0”, “1”, “2”and “3”) when the EEPROM is a four-level storing EEPROM.

[0812] When the EEPROM is structured to store four-level data, fourwriting states are provided for one memory cell transistor M. The fourwriting states are distinguished from one another in accordance with thethreshold voltage of the memory cell transistor M.

[0813] As shown in FIG. 83, the state of data “0” in the EEPROM havingthe power supply voltage Vcc which is set to 3V is made to be the sameas the state after data has been erased. Thus, for example, a negativethreshold voltage is assigned. In a state of data “1”, a thresholdvoltage from, for example, 0.5V to 0.8V is assigned. In a state of data“2”, a threshold voltage from, for example, 1.5V to 1.8V is assigned. Ina state of data “3”, a threshold voltage from, for example, 2.5V to 2.8Vis assigned.

[0814] When data is read from the memory cell transistor M, three readvoltages VCG1R to VCG3R are applied to the control gate CG,sequentially.

[0815] Initially, reading voltage VCG1R is applied to the control gateCG. In accordance-with whether the memory cell transistor M turns on oroff, whether stored data is “0” or “1 or 2 or 3” is detected. Then,reading voltage VCG2R is applied so that whether stored data is “1” or“2 or 3” is detected. When reading voltage VCG3R is applied, whetherdata is “2” or “3” is detected. The reading voltages VCG1R, VCG2R andVCG3R are, for example, 0V, 1V and 2V, respectively.

[0816] Voltages VCG1V, VCG2V and VCG3V shown in FIG. 83 are voltagescalled verify read voltages which are used to detect (when a verifyingoperation is performed) whether or not data has been sufficientlywritten. The verify read voltage is applied to the control gate CG afterdata has been written. Whether or not the threshold voltage of thememory cell transistor M has been shifted to a range corresponding towritten data can be detected in accordance with whether or not thememory cell transistor M is turned on when the verify read voltage hasbeen applied to the control gate CG. By using this, whether or notsufficient writing has been performed is detected. The verify readvoltages VCG1V, VCG2V and VCG3V are, for example, 0.5V, 1.5V and 2.5V,respectively.

[0817]FIG. 84 is a diagram showing the structure of the data circuit 306shown in FIG. 82.

[0818] As shown in FIG. 84, the data circuit 306 is connected to the bitline BL through a transfer gate circuit 307. The data circuit 306includes a bit line precharge circuit 308 for precharging the bit lineBL, a bit line reset circuit 309 for resetting the bit line BL; a datacontroller 310 having a function for storing write data and read data, abit line write voltage controller 311 for setting the voltage of the bitline BL to the bit line write control voltage and a column gate circuit312 for connecting the data controller 310 and the data input/outputline I/O.

[0819] The three data controllers 310-1 to 310-3 respectively storewhether or not data “1” is written, whether or not data “2” is writtenand whether or not data “3” is written.

[0820] The column gate circuit 312 is formed of n-channel MOStransistors Qn1, Qn2 and Qn3. The n-channel MOS transistors Qn1, Qn2 andQn3 control the connection between the three data controllers 310-1 to310-3 and the three data input/output lines I/01, I/02 and I/03.

[0821] The column decoder 313 is formed of an inverter circuit I1 and aNAND circuit G1. The column decoder 313 outputs a column selectionsignal CSL and selects one or more data circuits 306-0 to 306-m inresponse to an address signal when the column activating signal CENB is“H” level.

[0822] In the data circuit 306 selected by the column decoder 313, thedata controllers 310-1 to 310-3 and the data input/output lines I/O1 toI/03 are connected to one another. As a result, write data can besupplied from the data input/output lines I/O1 to I/03 to the datacontrollers 310-1 to 310-3.

[0823]FIG. 85 is a table showing write data and potential levels of thedata input/output lines I/O1 to I/03.

[0824] Similarly, read data can be output from the data controllers310-1 to 310-3 to the data input/output lines I/O1 to I/O3.

[0825]FIG. 86 is a table showing read data and the potential levels ofthe data input/output lines I/O1 to I/03.

[0826] The bit line write voltage controllers 311-1 to 311-3 areprovided for each of the data controllers 310-1 to 310-3. The bit linewrite voltage controllers 311-1 to 311-3 respectively are connected tonode Nai of each of the data controllers-to 310-3. The node Nai (I=1, 2,3) is a reverse signal of node Nci for the data controllers 310-1 to310-3.

[0827] Each of the bit line write voltage controllers 311-1 to 311-3 isformed of n-channel MOS transistors Qn4 and Qn5, Qn6 and Qn7 and Qn8 andQn9. The bit line write voltage controllers 311-1 to 311-3 output BLwrite control voltages VBL1, VBL2 and VBL3 to the bit line BL inaccordance with data stored in the data controllers 310-1 to 310-3.

[0828] The bit line precharge circuit 308 is formed of a p-channel MOStransistor Qp1. The p-channel MOS transistor Qp1 electrically chargesthe bit line BL to the power supply voltage Vcc in response to bit lineprecharge signal PRE.

[0829] The EEPROM according to the present invention has the structuresuch that the bit line precharge circuit 308 serves as one of the bitline write voltage controllers. The bit line precharge circuit 308applies the power supply voltage Vcc to the bit line BL, the powersupply voltage Vcc being used as one of bit line write control voltagesVBL (voltage when “0” is written as described later). Therefore, the bitline write control voltage generator is not required to generate all ofthe four bit line write control voltages but it is required to generateonly three voltages. Therefore, the size of the circuit can be reduced.

[0830] A bit line reset circuit 309 is formed of a n-channel MOStransistor Qn10. A n-channel MOS transistor Qn10 electrically dischargesthe bit line BL to the ground voltage 0V in response to bit line resetsignal RESET.

[0831] The transfer gate circuit 307 is formed of n-channel MOStransistors Qn11, Qn12 and Qn13. The n-channel MOS transistors Qn11,Qn12 and Qn13 respectively control the electrical connection between thedata circuit 306 and the bit line BL in response to transfer gate drivesignal BLC.

[0832]FIG. 87 is an operation waveform showing a writing operation ofthe EEPROM having the data circuit 306 shown in FIG. 84.

[0833] Referring to FIG. 87, the writing operation which is performed bythe EEPROM according to the tenth embodiment will now be described suchthat a state where control gate CG2 is selected.

[0834] Initially, the bit line reset signal RESET is made to be “L”level so that the n-channel MOS transistor Qn10 is turned off and thebit line BL is brought to the floating state. Then, the bit lineprecharge signal PRE is made to be “L” level so that the p-channel MOStransistor Qp1 is turned on and the bit line BL is electrically chargedto voltage Vcc which is one of bit line write control voltages VBL. Ifvoltage drop corresponding to the threshold voltage of the n-channel MOStransistor Qn11 raises a problem, the transfer gate drive signal BLC isrequired to be raised. Then, the bit line precharge signal PRE is madeto be “H” level so that the bit line BL is again brought to the floatingstate. The voltage of the bit line BL in the floating state ismaintained at the voltage Vcc (for example, 3V). If the bit line writecontrol voltage VBL2 is made to be, for example, 2V, the bit line writecontrol voltage VBL2 is made to be, for example, 1V and the bit linewrite control voltage VBL3 is made to be, for example, 0V.

[0835] Then, the write control signals PRO1, PRO2 and PRO3 aresequentially made to be “H” level. When data “1” is written, then-channel transistor Qn5 is turned on and the n-channel transistors Qn7and Qn9 are turned off. Therefore, the voltage of the bit line BL ismade to be 2V (VBL1). Similarly, when data “2” is written, the n channeltransistor Qn7 is turned on and the n-channel transistors Qn5 and Qn9are turned off. Thus, the voltage of the bit line BL is made to be 1V(VBL2). When data “3” is written, the n-channel transistor Qn9 is turnedon and the n-channel transistors Qn5 and Qn7 are turned off. Therefore,the voltage of the bit line BL is made to be 0V (VBL3). When data “0” iswritten, the n-channel transistors Qn5, Qn7 and Qn9 are turned off.Therefore, the voltage of the bit line BL is not changed and maintainedat 3V (Vcc).

[0836] Then, the selection gate SG1 in the selected block is made to bethe power supply voltage Vcc, the non-selected control gates CG1, CG3and CG4 are made to be the control gate write control voltage VM (forexample, 10V), the selected control gate CG2 is made to be the controlgate write voltage VPP (for example, 18V) and the selection gate SG2 ismade to be 0V to perform writing.

[0837] As described above, the EEPROM according to the tenth embodimenthas the structure such that the bit line write control voltage VBL forwriting data “0” is applied as follows. Therefore, a circuit forgenerating the foregoing voltage is not required. That is, the bit lineprecharge circuit 308 is operated to previously electrically charge thebit line BL to the voltage Vcc. Then, the charged bit line BL is broughtto the floating state prior to making the voltage of the bit line BL tocorrespond to write data so as to maintain the potential of the bit lineBL in the charged level. The potential of the charged BL is as it isused as the BL write control voltage when data “0” is written.Therefore, the circuit for making the voltage of the bit line BL tocorrespond to writing of data “0” can be omitted.

[0838] If the bit line BL is not brought to the floating state when data“0” is written, a circuit for making the voltage of the bit line BL tobe a level corresponding to writing of data “0” is required in a casewhere nodes Na1, Na2 and Na3 are “L”. Therefore, the number oftransistors and that of wiring are increased and thus the area of thecircuit is increased. In this case, the technical requirement forraising the degree of integration cannot be satisfied.

[0839] However, the tenth embodiment is able to reduce the area of theforegoing circuit so that the technical requirement for raising thedegree of integration is satisfied.

[0840] The EEPROM according to the tenth embodiment may be modified asfollows.

[0841] The reason why the bit line write control voltage VBL is changedto correspond to write data is that the quantity of charge to be storedin the floating gate of the memory cell transistor M2 is made to bedifferent for write data. However, in consideration of the principle ofthe injection of the charge into the floating gate, the bit line writecontrol voltages VBL when data “1”, “2” and “3” are written may be thesame (for example, 0V) except a case where data “0” is written. In thiscase, the voltage to be applied to the control gate CG is changed inaccordance with write data or time (time generally called a “write pulsewidth”) in which the voltage is applied to the control gate CG ischanged in accordance with write data to obtain the same effect.

[0842] The bit line write control voltage for writing data “1” may bemade to be voltage VBL2 and the bit line write control voltage forwriting data “2” or “3” may be made to be voltage VBL3. Alternately, thebit line write control voltage for writing data “1” or “2” may be madeto be voltage VBL2 and the bit line write control voltage for writingdata “3” may be made to be voltage VBL3.

[0843] The operation shown in the operation waveform shown in FIG. 87 isperformed such that the write control signal PRO1 is made to be “H”level in a period from time t1 to time t2. When data “1” is written, thevoltage of the bit line BL is made to be the voltage VBL1. In a periodfrom time t3 to t4, the write control signal PRO2 is made to be “H”level. When data “2” is written, the voltage of the bit line BL is madeto be the foregoing voltage VBL2. In a period from time t5 to t6 thewrite control signal PRO3 is made to be “H” level. When data “3” iswritten, the voltage of the bit line BL is made to be the foregoingvoltage VBL3.

[0844] Another structure may be employed in which a common power sourceis employed for voltages VBL1, VBL2 and VBL3; and the common powersource applies the voltage VBL1 in the period from time t1 to t3, thevoltage VBL2 in the period from time t3 to t5 and the voltage VBL3 inthe period from time t5 to t7. As an alternative to this, a common writesignal is employed for the write signals PRO1, PRO2 and PRO3 tosimultaneously make all of the signals to be “H” in only the period fromtime t1 to t2.

[0845] The voltage for the bit line BL, which is previously electricallycharged so as to be brought to the floating state may be another voltagelevel in place of Vcc. For example, the voltage of the bit line BL,which is previously electrically charged, may be 2V, 1V or 0Vcorresponding to data “1”, data “2” or data “3”. In this case, it ispreferable that a structure be employed in which the existing circuits,such as the verify circuit and the bit line reset circuit, connected tothe bit line BL are used to electrically charge the bit line BL to thevoltage level corresponding to data. In this case, enlargement of thecircuit can be prevented.

[0846] An example of the structure of the circuit for use in the datacontroller 310 will now be described.

[0847]FIG. 88A is a diagram showing the data controller 310 of thesemiconductor memory device according to the tenth embodiment of thepresent invention.

[0848] As shown in FIG. 88A, a data control circuit 310-i (i=1, 2 or 3)includes an input/output terminal 315 connected to a node Nai, aflip-flop circuit 314 i having a inverse input/output terminal 315Bconnected to a node Nci and a verify circuit 316 i.

[0849] The signal levels in the flip-flop circuit 314 i and the inverseinput/output terminal 315B have opposite phase to that of the signallevel of the input/output terminal 315. The inverse input/outputterminal 315B of the flip-flop circuit 314 i is electrically connectedto the data input/output line I/O and the bit line BL. Therefore, theflip-flop circuit 314 i is able to store information of data to bewritten in the memory cell and information of data to be read from thememory cell.

[0850] The verify circuit 316 i is formed of p-channel MOS transistorQp2 and Qp3. The potential of the node Nai is applied to the gate of thep-channel MOS transistor Qp2, while verify signal VRFYBi is supplied tothe gate of the p-channel MOS transistor Qp3. The verify circuit 316 iapplies the power supply voltage Vcc when the verify signal VRFYBi hasbeen made to be “L” in a case where the node Nai (i=1, 2 or 3) is “L”.

[0851] The n-channel MOS transistor Qn14, in series, connected betweenthe node Nci and the node Nai is a transfer gate circuit for controllingthe electrical connection between the node Nci and the node Nbi inresponse to transfer gate drive signal RVi (i=1, 2 or 3). When thetransfer gate drive signal has been made to be “H” level, the node Nciand the node Nbi are electrically connected.

[0852]FIG. 88B is a circuit diagram of the flip-flop circuit 314 i shownin FIG. 88A. The flip-flop circuit 314 i is formed of p-channel MOStransistors Qp4, Qp5, Qp6 and Qp7 and the n-channel MOS transistorsQn15, Qn16, Qn17 and Qn18. When data is written, write data informationis latched. When data is read, the potential of the bit line is sensedand read data information is latched.

[0853]FIG. 89 is an operation waveform of the EEPROM having the datacontrol circuit 310 i shown in FIG. 88A showing the reading operationand the verify read operation to be performed after the writingoperation.

[0854] Referring to FIG. 89, the reading and verify operations which areperformed by the EEPROM according to the tenth embodiment will now bedescribed such that the state in which the control gate CG2 has beenselected is taken for example.

[0855] Initially, the bit line reset signal RESET is made to be “L” sothat the bit line BL is brought to the floating state. Then, the bitline precharge signal PRE is made to be “L” level so that the bit lineBL is electrically charged to the power supply voltage Vcc. Then, thebit line precharge signal PRE is made to be “H” so that the bit line BLis again brought to the floating state.

[0856] When the usual reading operation is performed, read voltage VCGiR(i=1, 2 or 3) is applied to the selected control gate CG2. An example ofthe read voltage VCGiR is shown in FIG. 83. The non-selected controlgates CG1, CG3 and CG4 and the selection gates SG1 and SG2 are appliedwith the voltage Vcc.

[0857] When the verify read operation is performed, verify read voltageVCGiV (i=1, 2 or 3) is applied to the selected control gate CG2. Anexample of the verify read voltage VCGiV is shown in FIG. 83 similarlyto the read voltage VCGiR. When the verify read operation is performed,also the voltage Vcc is applied to the non-selected control gates CG1,CG3 and CG4 and the selection gates SG1 and SG2.

[0858] When the foregoing usual reading operation or verify readoperation is performed, the potential of the bit line BL is made to be“L” level if the threshold voltage of the memory cell transistor M2 isnot higher than the read voltage VCGiR or not higher than the verifyread voltage VCGiV. If the threshold voltage of the memory celltransistor M2 is not lower than the read voltage VCGiR or not lower thanthe verify read voltage VCGiV, the potential of the bit line is made tobe “H” level.

[0859] When the verify read operation is then performed, the verifysignal VRFYBi is made to be “L” level as indicated by a broken line.Only when the node Nai is “L” level, the potential of the bit line BL ismade to be “H” level regardless of the state of the memory celltransistor M2. Then, the sense amplifier activating signal SENi is madeto be “L” level, SENBi is made to be “H” level, the latch activatingsignal LATi is made to be “L” level and LATBi is made to be “H” level.Thus, the flip-flop circuit 314 i is deactivated. After the flip-flopcircuit 314 i has been deactivated, the transfer gate drive signal RViis made to be “H” level so that the nodes Nbi and the node Nci areelectrically connected to each other. After the node Nbi and the nodeNci have been electrically connected to each other, the sense amplifieractivating signal SENi is made to be “H” level and SENBi is made to be“L” level so that the flip-flop circuit 314 i is activated. Since theflip-flop circuit 314 i has been activated and connected to the bit lineBL, the voltage of the bit line BL is sensed. Then, the latch activatingsignal LATi is made to be “H” level and LATBi is made to be “L” level sothat the voltage (information) of the sensed bit line BL is latched bythe flip-flop circuit 314 i.

[0860] The voltage of the bit line BL indicated as (*1) is the voltagewhen the threshold voltage of the memory cell transistor is VCGi orhigher, that indicated as (*2) is the voltage when the threshold voltageof the memory cell transistor is VCGi or lower and that indicated as(*3) is the voltage when the node Nai is “L” level when verify readoperation is performed.

[0861] The foregoing operation is repeated in the data controllers 310-1to 310-3 so that reading of data and verify read of written data areperformed.

[0862] The data controller 310-1 detects whether data stored in thememory cell transistor M is “1” or “2” or “3” when the usual readingoperation is performed. When the verify read operation is performed, thedata controller 310-1 detects whether or not data written in the memorycell transistor M has reached the state “1”. Similarly, the datacontroller 310-2 detects whether data stored in the memory celltransistor M is “2” or “3” when the usual reading operation isperformed. When the verify read operation is performed, the datacontroller 310-2 detects whether or not data written in the memory celltransistor M has reached the state “2”. The data controller 310-3detects whether or not data stored in the memory cell transistor M is“3” when the usual reading operation is performed. When the verify readoperation is performed, the data controller 310-3 detects whether or notdata written in the memory cell transistor M has reached the state “3”.

[0863] Another example of the structure of the data controller 310 willnow be described.

[0864]FIG. 90A is a diagram showing another structure of the datacontroller 310 of the semiconductor-memory device according to the tenthembodiment of the present invention.

[0865] As shown in FIG. 90A, the data controller 310A-i (i =1, 2 or 3)has an input/output terminal 315 connected to the node Nai, a flip-flopcircuit 314Ai having an inverse input/output terminal 315B connected tothe node Nci and a data transfer controller 317 i (i=1, 2 or 3) forcontrolling transfer of data in the bit line BL to the flip-flop circuit314Ai.

[0866] The signal level of the inverse input/output terminal 315B of theflip-flop circuit 314Ai has an opposite phase of the signal level of theinput/output terminal 315. The input/output terminal 315 of theflip-flop circuit 314Ai is connected to the data transfer controller 317i, while the inverse input/output terminal 315B is connected to the datainput/output line I/O. Therefore, the flip-flop circuit 314Ai is able tostore information of data to be written in the memory cell andinformation of data read from the memory cell, similarly to theflip-flop circuit 314 i shown in FIGS. 88A and 88B.

[0867] The data transfer controller 317i is formed of p-channel MOStransistor Qp8 and n-channel MOS transistors Qn19 and Qn20, in seriesconnected between the power supply voltage Vcc and the ground potentialVss. The p-channel MOS transistor Qp8 resets the node Nai to “H” whensignal LTRSTi has been made to be “L” level. The n-channel MOStransistors Qn19 and Qn20 make the node Nai to “L” level when thepotential of the node Nbi is “H” level and signal DTCi is “H” level.

[0868]FIG. 90B is a diagram of a circuit for use in the flip-flopcircuit 314Ai shown in FIG. 90A. The flip-flop circuit 314Ai is formedof a cross couple type latch in which the output of a CMOS inverter I2is connected to the input of a CMOS inverter I3 and the output of theCMOS inverter I3 is connected to the input of the CMOS inverter I2.

[0869]FIG. 91 is an operation waveform for the EEPROM having the datacontroller 314 i shown in FIG. 90A showing the reading operation and theverify operation which is performed after the writing operation has beenperformed.

[0870] Referring to FIG. 91, the reading operation and the verify readoperation which are performed by the EEPROM will now be described suchthat a state in which the control gate CG2 has been selected is takenfor example.

[0871] Initially, the bit line reset signal RESET is made to be “L”level so that the bit line BL is brought to the floating state. When ausual reading operation is performed, the signal LTRSTi is made to be“L” level, while the node Nai is reset to “H” level. Then, the bit lineprecharge signal PRE is made to be “L” level and the bit line BL iselectrically charged to the power supply voltage Vcc. Then, the bit lineprecharge signal PRE is made to be “H” level so that the bit line BL isagain brought to the floating state.

[0872] When a usual reading operation is then performed, the readvoltage VCGiR (i=1, 2 or 3) is applied to the selected control gate CG2.An example of the read voltage VCGiR is shown in FIG. 83. Thenon-selected control gates CG1, CG3 and CG4 and the selection gates SG1and SG2 are applied with the voltage Vcc.

[0873] When the verify read is performed, the verify read voltage VCGiV(i=1, 2 or 3) is applied to the selected control gate CG2. An example ofthe verify read voltage VCGiV is, similarly to the read voltage VCGiR,shown in FIG. 83. When the verify read is performed, the voltage Vcc isapplied to the non-selected control gates CG1, CG3 and CG4 and theselection gates SG1 and SG2.

[0874] When the usual reading or verify read is performed, the potentialof the bit line BL is made to be “L” level if the threshold voltage ofthe memory cell transistor M2 is not higher than the read voltage VCGiRor not higher than the verify read voltage VCGiV. If the, thresholdvoltage of the memory cell transistor M2 is not lower than the readvoltage VCGiR or not lower than the verify read voltage VCGiV, thepotential of the bit line BL is made to be “L” level.

[0875] When the verify read operation is then performed, the n-channelMOS transistor Qn19 is turned on in only a case where the signal DTCi ismade to be “H” and the potential of the bit line BL is “H” level.Therefore, the potential of the node Nai is made to be “L” level. If thepotential of the bit line BL is “L” level, the n-channel MOS transistorQn19 is turned off. Therefore, the potential of the node Nai is notchanged.

[0876] The voltage of the bit line BL indicated as (*4) is the voltagewhen the threshold voltage of the memory cell transistor is not lowerthan VCGi, and the voltage indicated as (*5) is the voltage when thethreshold .voltage of the memory cell transistor is not higher thanVCGi. The voltage of the node Nai when the usual reading is performedand indicated as (*6) is the voltage when the threshold voltage of thememory cell transistor is not higher than VCGi and the voltage indicatedas (*7) is the voltage when the threshold voltage of the memory celltransistor is not lower than VCGi. The voltage of the node Nai when theverify read is performed and indicated as (*8) is the voltage when thethreshold voltage of the memory cell transistor is not higher than VCGiand the voltage indicated as (*9) is the voltage when the thresholdvoltage of the memory cell transistor is not lower than VCGi.

[0877] The foregoing operation is repeated in the data controllers310A-1 to 310A-3 so that reading of data and verify read of written dataare performed. The data controller 310A-1 detects whether data stored inthe memory cell transistor M is “1” or “2” or “3” when the usual readingoperation is performed. When the verify read operation is performed, thedata controller 310A-1 detects whether or not data written in-the memorycell transistor M has reached the state “1”. Similarly, the datacontroller 310A-2 detects whether data stored in the memory celltransistor M is “2” or “3” when the usual reading operation isperformed. When the verify read operation is performed, the datacontroller 310A-2 detects whether or not data written in the memory celltransistor M has reached the state “2”. The data controller 310A-3detects whether or not data stored in the memory cell transistor M is“3” when the usual reading operation is performed. When the verify readoperation is performed, the data controller 310A-3 detects whether ornot data written in the memory cell transistor M has reached the state“3”.

[0878] If the data controller 310 shown in FIG. 84 is formed of thecircuit shown in FIG. 88A or the circuit shown in FIG. 90A, repetitionof the writing operation and the verify read operation causes four-leveldata to be written in the memory cell transistor M. When data has beenwritten in all of the memory cells forming the page, data written in allof the data circuits 306-0 to 306-m is made to be “0”. The reason forthis is that write data is changed as shown in FIG. 92 if success ofwriting has been confirmed as a result of the verify read.

[0879]FIG. 92 is a table showing a state of change of data in the datacircuit 306. If results of the detection of write data in all of thedata circuits 306-0 to 306-m are “0” level, the data writing operationis completed. The writing operation is performed after a fact that datahas sufficiently reached a required state has been confirmed.

[0880]FIG. 93 is a circuit diagram showing a data write completiondetecting circuit 318 for detecting write data in the data circuit 306to detect whether or not data write operation has been completed.

[0881] As shown in FIG. 13, the data write completion detecting circuit318 is provided for each data circuit 306. Detection circuits 318-1 to318-m respectively detect write data for the data circuits 306-0 to306-m. When all of the data items are “0” level, a data write completionsignal is output.

[0882] Each of the detection circuits 318-1 to 318-m is formed ofn-channel MOS transistors Qn100 to Qn105. The n-channel MOS transistorsQn100 and Qn101 detect whether or not the node Na1 of the datacontroller 310-1 is “L” level. The n-channel MOS transistors Qn102 andQn103 detect whether or not the node Na2 of the data controller 310-2 is“L” level. The n-channel MOS transistors Qn104 and Qn105 detect whetheror not the node Na3 of the data controller 310-3 is “L” level. When allof the signals PCHK1, PCHK2 and PCHK3 are “H” and all of the signallines PEND1, PEND2 and PEND3 are not electrically connected to theground potential Vss, a data write completion signal is output and thedata write is completed. Although the signals PCHK1, PCHK2 and PCHK3 aredifferent signals in this embodiment, a common signal may be employed.Although the signal lines PEND1, PEND2 and PEND3 are different signallines in this embodiment, a common signal line may be employed.

[0883] (Eleventh Embodiment)

[0884] A multilevel storing EEPROM according to an eleventh embodimentof the present invention will now be described. In this description, thesame elements as those of the EEPROM according to the tenth embodimentare given the same reference numerals and different portions will mainlybe described.

[0885]FIG. 94 is a diagram showing the structure of a data circuit ofthe multilevel storing EEPROM according to the eleventh embodiment ofthe present invention.

[0886] The EEPROM according to the eleventh embodiment and thataccording to the tenth embodiment are different from each other in astructure in which the data controllers 310-1 to 310-3 included in thedata circuit 306 are arranged to be dispersed at the two ends of the bitline BL.

[0887] Another difference lies in that the controller (311-3) of thethree bit line write voltage controllers 311 for outputting a bit linewrite control voltage VBL3 which is 0V is omitted. Moreover, the output(0V) of “L” level from the flip-flop circuit included in the datacontroller 310-3 is used as the voltage VBL3.

[0888] Further difference lies in that the “H” level output (Vcc=3V)from the flip-flop circuit included in the data controller 310-3 is usedas the bit line write control voltage VBL for writing data “0”.

[0889] Note that the data controllers 310-1 to 310-3 shown in FIG. 94are the same as the data controllers 310-1 to 310-3 shown in FIG. 88A.

[0890]FIG. 95 is an operation waveform showing the write operation whichis performed by the EEPROM having the data circuit shown in FIG. 94.

[0891] Referring to FIG. 95, the write operation, which is performed bythe EEPROM according to the eleventh embodiment, will now be describedsuch that a state in which the control gate CG2 has been selected istaken for example.

[0892] Initially, the bit line reset signal RESET is made to be “L”level so that the bit line BL is brought to the floating state. Then,the transfer gate drive signal RV3 is made to be “H” level and theverify signal VRFYB3 is made to be “L” level. When data “0” or data “1”or data “2” is written, an “H” level output is supplied to the bit lineBL from the flip-flop circuit 314-3. Thus, the bit line BL iselectrically charged to the voltage Vcc which is one of bit line writecontrol voltages VBL. When data “3” is written, an “L” level output issupplied to the bit line BL from the flip-flop circuit 314-3. The bitline BL is made to be 0V which is another voltage of the bit line writecontrol voltages VBL. Then, the transfer gate drive signal RV3 is madeto be “L” level and the verify signal VRFYB3 is made to be “L” level sothat the bit line BL is again brought to the floating state.

[0893] Then, the write control signals PRO1 and PRO2 respectively aremade to be “H” level. When data “1” is written, the n-channel transistorQn5 is turned on and Qn7 is turned off so that the voltage of the bitline BL is made to be 2V (VBL1). When data “2” is written, the n-channeltransistor Qn5 is turned off and Qn7 is turned on so that the voltage ofthe bit line BL is made to be 1V (VBL2). When data “3” is written, bothof the n-channel transistors Qn5 and Qn7 are turned off so that thevoltage of the bit line BL is not changed and maintained at 0V. Whendata “0” is written, both of the n-channel transistors Qn5 and Qn7 areturned off so that the voltage of the bit line BL is not changed andmaintained at the voltage Vcc.

[0894] Then, the selected gate SG1 in the selected block is made to bethe power supply voltage Vcc, the non-selected control gates CG1, CG3and CG4 are made to be the control gate write control voltage VM (forexample, 10V), the selected control gate CG2 is made to be the controlgate write voltage VPP9 (for example, 18V) and the selected gate SG2 ismade to be 0V when writing is performed.

[0895] The reading operation and the verify read operation, which isperformed after the writing operation are performed as shown in FIG. 89or FIG. 91.

[0896] As described above, the EEPROM according to the eleventhembodiment has the structure such that the bit line write controlvoltage VBL for writing data “0” is used to previously electricallycharge the bit line BL to the voltage Vcc by using the “H” level outputfrom the flip-flop circuit 314-3. Similarly, the bit line write controlvoltage VBL for writing data “3” is used to previously electricallycharge the bit line BL by using the “L”level output from the flip-flopcircuit 314-3. Prior to making the voltage of the bit line BL to thevoltage corresponding to write data, charged or discharged bit line BLis brought to the floating state so as to maintain the potential of thebit line BL at the charged or discharged state. The potential of the bitline BL in the charged state is as it is used as the bit line writecontrol voltage when data “0” is written. Similarly, the potential ofthe bit line BL in the discharged state is as it is used as the bit linewrite control voltage when data “3” is written.

[0897] Therefore, also the eleventh embodiment is able to omit thecircuit for making the voltage of the bit line BL to be the voltagecorresponding to writing of data Moreover, the eleventh embodiment isable to omit the circuit for making the voltage of the bit line BL to bethe voltage corresponding to writing of data “3”.

[0898] Therefore, the eleventh embodiment is able to solve the problemin that the area of the circuit is increased excessively similarly tothe tenth embodiment. Thus, the technical requirement for raising thedegree of integration can be satisfied.

[0899] Note that the EEPROM according to the eleventh embodiment may bemodified similarly to the EEPROM according to the tenth embodiment.

[0900] Although the bit line write control voltages VBL1 and VBL2 aredetermined to be 2V and 1V, the voltages may be 0V.

[0901] (Twelfth Embodiment)

[0902] A multilevel storing EEPROM according to a twelfth embodiment ofthe present invention will now be described.

[0903]FIG. 96 is a diagram showing the structure of the multilevelstoring EEPROM according to the twelfth embodiment of the presentinvention.

[0904] The EEPROM structured as shown in FIG. 96 and according to thetwelfth embodiment is different from the EEPROM having the structureshown in FIG. 81, the EEPROM according to this embodiment having astructure called an open bit structure. The open bit structure basicallycomprises row-system circuits 302 a and 302 b provided for memory cellarrays 310 a and 310 b and a column-system circuit 303 which is commonlyprovided for the memory cell arrays 310 a and 310 b.

[0905] The row-system circuits 302 a and 302 b include a row decoder302A for receiving an address signal output from the address buffer 304and selects a row in the memory cell array in response to the suppliedaddress signal and a word line driver 302B for driving a word line ofthe memory cell array in accordance with an output from the row decoder302A. In the case of a NAND type EEPROM of a type according to thisembodiment, the word line is a selection gate and a control gate.Therefore, the word line driver 302B is also called a controlgate/selection gate driver.

[0906] The column-system circuit 303 which is commonly used by thememory cell arrays 301 a and 301 b has a column decoder 303A forreceiving the address signal output from the address buffer 304 toselect a column in the memory cell array in response to the suppliedaddress signal, and a column selection line driver 303B for driving acolumn selection line for selecting a column of the memory cell array inaccordance with an output from the column decoder 303A. Moreover, thecolumn-system circuit 303 has a bit line controller 303C including adata circuit for temporarily storing data to be written in the memorycell and reading data in the memory cell. The bit line controller 303Cis connected to a data input/output circuit (data input/output buffer)305. The bit line control circuit 303C receives read data from thememory cell when data is read to output the supplied read data to thedata input/output buffer 305.

[0907] The data input/output buffer 305 controls input and output ofdata such that it introduces write data supplied from outside of theEEPROM to a memory core portion and outputs data read from the memorycore portion to the outside of the EEPROM. The data input/output buffer305 has a function to serve as an interface circuit between the outsideof the EEPROM and the memory core portion. An example of the interfacecircuit function is such that two ternary data read from the memory coreportion is encoded into 3-bit data to output the same to the outside anda function for decoding supplied 3-bit data into two ternary data tointroduce the same to the memory core portion. In the description below,another interface circuit function will be described.

[0908]FIG. 97 is a diagram showing the structures of the memory cellarrays 301 a and 301 b and the column-system. circuit 303 shown in FIG.96.

[0909] As shown in FIG. 97, each of the memory cell arrays 301 a and 301b has memory cells MC arranged in the matrix manner. The EEPROMaccording to this embodiment has a structure such that one cell MCincludes a plurality of memory cell transistors connected in series sothat a NAND cell MC is formed. An end of the cell MC is connected to bitline BL through a selection transistor S1, while another end of the sameis connected to a source line VS through a selection transistor S2. Agroup of the memory cell transistors sharing the control gate CG forms aunit called a “page”. Data is written and read simultaneously in unit ofpage. A group of memory cell transistors M connected to four controlgates CG1 to CG4 forms a unit called a “block”. The page and blockrespectively are selected by control gate/selection gate driver. Datacircuits 306A-O to 306A-m respectively are connected between the bitlines BLa0 to BLam and data input/output line I/O. The data circuits306A-0 to 306A-m have a function for temporarily storing data to bewritten in the memory cell and a function for sensing and temporarilystoring data read from the memory cell.

[0910]FIG. 98 is a table showing the relationship between the thresholdvoltages of the memory cell transistor and three writing states (ternarydata “0”, “1” and “2”) when the EEPROM has a structure for storingternary data.

[0911] When the EEPROM is structured to store ternary data, threewriting states are provided for one memory cell transistor. The threewriting states are distinguished from one another in accordance with thethreshold voltage of the memory cell transistor M.

[0912] As shown in FIG. 98, the state of data “0” in the EEPROM havingthe power supply voltage Vcc which is set to 3V is made to be the sameas the state after data has been erased. Thus, for example, a negativethreshold voltage is assigned. In a state of data “1”, a thresholdvoltage from, for example, 0.5V to 0.8V is assigned. In a state of data“2”, a threshold voltage from, for example, 2.0V to 2.3V is assigned.

[0913] When data is read from the memory cell transistor, three readvoltages VCG1R to VCG2R are sequentially applied to the control gate CG.

[0914] Initially, reading voltage VCG1R is applied to the control gateCG. In accordance with whether the memory cell transistor turns on oroff, whether stored data is “0” or “1 or 2” is detected. Then, readingvoltage VCG2R is applied so that whether stored data is “1” or “2” isdetected. The reading voltages VCG1R and VCG2R are, for example, 0V and1.5V , respectively.

[0915] Voltages VCG1V and VCG2V shown in FIG. 98 are voltages calledverify read voltages which are used to detect (when a verifyingoperation is performed) whether or not data has been sufficientlywritten. The verify, read voltage is applied to the control gate CGafter data has been written. Whether or not the threshold voltage of thememory cell transistor has been shifted to a range corresponding towritten data can be detected in accordance with whether or not thememory cell. transistor is turned on when the verify read voltage hasbeen applied to the control gate CG. By using this, whether or notsufficient writing has been performed is determined. The verify readvoltages VCG1V and VCG2V are, for example, 0.5V and 2.5V, respectively.

[0916]FIG. 99 is a diagram showing the structure of the data circuit306A shown in FIG. 97.

[0917] As shown in FIG. 99, the data circuit 306A is connected to thebit line BLa through a transfer gate circuit 307A and is connected tothe bit line Blb through the transfer gate 307B. The transfer gatecircuit 307A is formed of n-channel MOS transistor Qn36 so as to controlthe connection between the data circuit 306A and the bit line BLa inresponse to transfer gate drive signal BLCA. The transfer gate circuit307B is formed of an n-channel MOS transistor Qn37 to control theconnection between the data circuit 306A and the bit line BLb inresponse to the transfer gate drive signal BLCA. The data circuit 306Aincludes a bit line precharge circuit 308A for precharging the bit lineBLa, a bit line precharge circuit 308B for precharging the bit line BLb,a data controller 310A having a function for storing write data and readdata, a column gate circuit 312 for connecting the data controller 310Aand the data input/output line I/O, an equalizer 321-1 for equalizing anode N3 of the data controller 310A connected to the data input/outputline I/OA and a node N4 of the data controller 310A connected to thedata input/output line I/OB and an equalizer 321-2 for equalizing a nodeN5 of the data controller 310A connected to the data input/output lineI/OC and a node N6 of the data controller 310A connected to the datainput/output line I/OD.

[0918] The bit line precharge circuit 308A is formed of the n-channelMOS transistor Qn38. Similarly, the bit line precharge circuit 308B isformed of the n-channel MOS transistor Qn39. The n-channel MOStransistor Qn38 electrically charges the bit line BLa to the voltage VAin response to the bit line precharge signal PREA. Similarly, then-channel MOS transistor Qn39 electrically charges the bit line BLb inresponse to the bit line precharge signal PREB.

[0919] The column gate circuit 312 is formed of the n-channel MOStransistors Qn28, Qn29, Qn30 and Qn31. The n-channel MOS transistorsQn28, Qn29, Qn30 and Qn31 control the connection between the datacircuit 306A and the data input/output lines I/OA to I/OD. An end of thedata input/output line I/OA is, through the n-channel MOS transistorQn28, connected to the node N3. An end of the data input/output lineI/OB is, through the n-channel MOS transistor Qn29, connected to thenode N4. An end of the data input/output line I/OC is, through then-channel MOS transistor Qn30, connected to the node N5. An end of thedata input/output line I/OD is, through the n-channel MOS transistorQn31, connected to the node N6. Another end of each of the datainput/output lines I/OA to I/OD is connected to the data input/outputbuffer 305 shown in FIG. 96.

[0920] In the data circuit 306A selected by the column decoder 313, thedata controller 310A and the data input/output lines I/OA to I/OD areconnected to one another. As a result, write data can be supplied fromthe data input/output lines I/OA to I/OD to the data controller 310A.

[0921]FIG. 103 is a table showing write data for writing data andpotential levels of the data input/output lines I/OA to I/OD.

[0922] Similarly, read data can be output from the data controller 310Ato the data input/output lines I/OA to I/OD.

[0923]FIG. 104 is a table showing read data when data is read and thepotential levels of the data input/output lines I/OA to I/OD.

[0924] The equalizer 321-1 is formed of the n-channel MOS transistorQn40 to equalize the node N3 and the node N4 in response to theequalizing signal ECH1. Similarly, the equalizer 321-2 is formed of then-channel MOS transistor Qn43 to equalize the node N5 and the node N6 inresponse to the equalizing signal equalizing signal ECH2.

[0925] The EEPROM according to the twelfth embodiment has a structuresuch that each of the bit line precharge circuits 308A and 308B servesone of bit line write voltage controllers. The voltage VA which isapplied from the bit line precharge circuit 308A to the bit line BLa isused as one of bit line write control voltages VBL. Similarly, thevoltage VB which is applied from the bit line precharge circuit 308B tothe bit line BLb is used as one of bit line write control voltages VBL.

[0926] An example of the data controller 310A will now be described.

[0927]FIG. 100 is a diagram showing the structure of the data controller310A of the semiconductor memory device according to the twelfthembodiment of the present invention. FIG. 101 is a circuit diagramshowing a first flip-flop circuit. FIG. 102 is a circuit diagram showinga second flip-flop circuit.

[0928] As shown in FIG. 100, the data controller 310A includes a firstflip-flop circuit 314A-1 having an input/output terminal connected tothe node N3 and an inverted input/output terminal connected to the nodeN4, a second flip-flop circuit 314A-2 having an input/output terminalconnected to the node N5 and an inverted input/output terminal connectedto the node N6 and a verify circuit 316A.

[0929] As shown in FIG. 101, the first flip-flop circuit 314A-1 isformed of n-channel MOS transistors Qn22, Qn23 and Qn24 and p-channelMOS transistors Qp9, Qp10 and Qp11. As shown in FIG. 102, the secondflip-flop circuit 314A-2 is formed of the n-channel MOS transistorsQn25, Qn26 and Qn27 and p-channel MOS transistors Qp12, Qp13 and Qp14.The first flip-flop circuit 314A-1 and the second flip-flop circuit314A-2 latch information of data to be written when data is written,sense the potential of the bit line BLa or bit line BLb and latch readdata information when data is read.

[0930] The first flip-flop circuit 314A-1 latches write data informationwhether or not data “0” is written in the memory cell transistor andwhether “1” or “2” is written. As read data information, it senses andlatches whether or not the memory cell transistor stores data “0” andwhether or not the same stores data “1” or “2”.

[0931] The second flip-flop circuit 314A-2 latches, as write datainformation, whether or not data “2” is written in the memory celltransistor and whether or not “1 or 0” is written. As read datainformation, it senses and latches whether or not the memory celltransistor stores data “2” and whether or not it stores. “1 or 0”.

[0932] The n-channel MOS transistors Qn32, Qn33, Qn34 and Qn35respectively form transfer gate circuits. The n-channel MOS transistorQn32 connects the node N3 of the first flip-flop circuit 314A-1 to theMOS capacitor Qd1 connected to the node N1 when the transfer gate drivesignal RV1A has been made to be “H” level. The n-channel MOS transistorQn33 connects the node N5 to the second flip-flop circuit 314A-2 to theMOS capacitor Qd1 when the transfer gate drive signal RV2A has been madeto be “H” level. The n-channel MOS transistor Qn34 connects the node N4of the first flip-flop circuit 314A-1 to the MOS capacitor Qd2 connectedto the node N2 when the transfer gate drive signal RV1B has been made tobe “H” level. The n-channel MOS transistor Qn35 connects the node N6 ofthe second flip-flop circuit 314A-2 to the MOS capacitor Qd2 when thetransfer gate drive signal RV2B has been made to be “H” level. The MOScapacitors Qd1 and Qd2 are formed of depletion type n-channel MOStransistors each having a capacity which is sufficiently smaller thanthe capacity of the bit line.

[0933] The verify circuit 316A is formed of the p-channel MOStransistors Qp12, Qp13, Qp14 and Qp15.

[0934] The p-channel MOS transistor Qp14 forming the verify circuit 316Ais electrically conducted when the activating signal VRFYBA has beenmade to be “L” level. The p-channel MOS transistor Qp15 is electricallyconducted when the node N4 of the first flip-flop circuit 314A-1 hasbeen made to be “L” level. When both of the p-channel MOS transistorsQp14 and Qp15 have been electrically conducted, the gate of the MOScapacitor Qd1, that is, the node N1 ₁, is applied with the voltage Vcc.The p-channel MOS transistor Qp12 forming the verify circuit 316A iselectrically conducted when the activating signal VRFYBB has been madeto be “L” level. The p-channel MOS transistor Qp13 is electricallyconducted when the node N3 of the first flip-flop circuit 314A-1 hasbeen made to be “L” level. When both of the p-channel MOS transistorsQp12 and Qp13 are electrically conducted, the gate of the MOS capacitorQd2, that is, the node N2, is applied with the voltage Vcc.

[0935] When the n-channel MOS transistor Qn38 shown in FIG. 99 has beenelectrically conducted, the gate of the MOS capacitor Qd1 is appliedwith the voltage VA so that the MOS capacitor Qd1 is electricallycharged. When the n-channel MOS transistor Qn39 shown in FIG. 99 hasbeen electrically conducted, the gate of the MOS capacitor Qd2 isapplied with the voltage VB so that the MOS capacitor Qd2 iselectrically charged.

[0936] As described above, the bit line precharge circuits 308A and 308Bformed of the n-channel MOS transistors Qn38 and Qn39 also serve as bitline write voltage controllers.

[0937] Also the verify circuit 316A for changing the gate voltages ofthe MOS capacitors Qd1 and Qd2 is a circuit also serving as a bit linewrite voltage controller.

[0938] Also the transfer gate circuit formed of the second flip-flopcircuit 314A-2 and the n-channel MOS transistor Qn33 and the transfergate circuit formed of the n-channel MOS transistor Qn35 change the gatepotentials of the MOS capacitors Qd1 and Qd2. Therefore, the foregoingcircuits also serve as bit line write voltage controllers.

[0939] The operation of the EEPROM according to the twelfth embodimentof the present invention will now be described. An operation will now bedescribed in which an access to the memory cell array 301 a of the twomemory cell arrays 301 a and 301 b has been made and thus the controlgate CG2A has been selected. Since the operation which is performed whenan access to the memory cell array 301 b has been made is similar to theoperation which is performed when an access to the memory cell array 301a has been made, it is omitted from description.

[0940]FIG. 105 is an operation waveform showing a writing operationwhich is performed by the EEPROM according to the twelfth embodiment ofthe present invention.

[0941] Initially, for example, 3-bit external write data is supplied tothe data input/output buffer 305 from outside of the EEPROM. The 3-bitexternal write data is eight-level data. The memory cell transistor ofthe EEPROM according to this embodiment has a structure for storingternary data. Therefore, external write data is converted into twoternary effective data items in the EEPROM by the data input/outputbuffer 305. Each of the ternary data items is expressed, for example, asshown in FIG. 103 and supplied to the data circuit 306A. Two ternaryeffective data items are prepared so as to be supplied to the datacircuit 306A in the adjacent even and odd-order columns. Thus, the 3-biteight-level data items are, by the data input/output buffer 305,converted into ternary data×2, that is, nine-levels as the-level of datasuch that eight of the nine-levels are effective. One of the two ternarydata items which are internally effective is transferred to one of thedata circuits 306A corresponding to the column address instructed withthe address signal when the column activating signal CENB is “H” level.Any one of the ternary data items is, as write data, stored in the datacircuit 306A.

[0942] Then, the bit line precharge signal PREA is made to be “H” leveland the voltage VA is made to be 1.5V. As a result, the bit line BLa iselectrically charged to 1.5V which is one of bit line write controlvoltages. Then, the bit line precharge signal PREA is made to be “L” sothat the bit line BLa is brought to the floating state. Then, the verifysignal VRFYBA is made to be “L” level and the transfer gate drive signalRVA2A is made to be 1.5V. When the threshold voltage of the n-channelMOS transistor Qn33 having a gate for receiving the drive signal RVA2Ais made to be 1V, the n-channel MOS transistor Qn33 is turned off whendata “0” or data “1” is written and turned on when data “2” is written.As a result, when the data controller 310A stores data “0”, voltage Vccis, as the bit line write control voltage, applied from the datacontroller 310A to the bit line BLa. When the data controller 310Astores data “2”, voltage Vss (0V) is, as the bit line write controlvoltage, applied from the data controller 310A to the 3-bit line BLa. Ifa problem arises in that the potential of the bit line BLa is dropped bya degree corresponding to the threshold voltage of the n-channel MOStransistor Qn36 in the transfer gate circuit 307A (see FIG. 99), thedrive signal BLCA is required to be raised to the raised potential VM,as shown in FIG. 105. The bit line voltage BLa indicated as (*1) isvoltage when data “0” is written, the voltage indicated as (*2) isvoltage when data “1” is written and the voltage indicated as (*3) isvoltage when data “2” is written.

[0943] Then, the control gate/selection gate driver 303B makes thepotentials of the selection gate SG1A and the control gates CG1A to CG4Ain the selected block to be voltage Vcc. The selection gate SG2A is 0V.Then, the selected control gate CG2A is made to be high voltage VPP (forexample, 20V), and the non-selected control gates CG1A, CG3A and CG4Aare made to be intermediate voltage VM (for example, 10V). In the memorycell transistor corresponding to the data controller 310A storing data“2”, the difference in the potential between the channel potential of 0Vand VPP of the control gate causes electrons to be injected into thefloating gate so that the threshold voltage is increased. In the memorycell transistor corresponding to the data controller 310A storing data“1”, the difference in the potential between the channel potential of1.5V and VPP of the control gate causes electrons to be injected intothe floating gate so that the threshold voltage is increased. The reasonwhy the channel potential is made to be 1.5V is that the quantity ofelectrons to be injected into the floating gate is required to bereduced as compared with the case in which data “2” is written. In thememory cell transistor corresponding to the data controller 310A storingdata “0”, the difference in the potential between the channel potentialand VPP for the control gate is small. Therefore, substantially noelectrons is injected into the floating gate. Therefore, the thresholdvoltage of the memory cell transistor is not changed.

[0944] During the writing operation, the sense amplifier activatingsignals SAN1 and SAN2, the verify signal VRFYBB, the bit line prechargesignal PREB and the transfer gate drive signal BLCB are “H” level. Thesense amplifier activating signals SAP1 and SAP2, the transfer gatedrive signals RV1A, RV1B and RV2B and the equalizing signals ECH1 andECH2 are “L” level. The voltage VB is 0V.

[0945] After the writing operation has been completed, the verify readoperation is performed to verify the threshold voltage of the memorycell transistor. If a fact that the threshold voltage of the memory celltransistor has reached a required-level has been verified as a result ofthe verify read operation, read data stored by the data controller 310Ais changed to data “0”. If it has not reached the required-level, thedata controller 310A again performs the writing operation whilemaintaining stored write data. The write operation and the verify readoperation are repeated until all of the threshold voltages of theselected memory cell transistors reach the required levels.

[0946]FIG. 106 is an operation waveform showing the reading operationwhich is performed by the EEPROM according to the twelfth embodiment ofthe present invention.

[0947] Initially, the voltage VA is made to be 1.8V and the voltage VBis made to be 1.5V. As a result, the bit line BLa is electricallycharged to 1.8V and the bit line BLb is electrically charged to 1.5V.Then, the transfer gate drive signals BLCA and BLCB are made to be “L”level so that the-bit line BLa and the MOS capacitor Qd1 are separatedfrom each other and the bit line BLb and the MOS capacitor Qd2 areseparated from each other. As a result, the bit lines BLa and BLb arebrought to the electrically floating state.

[0948] Then, the bit line precharge signals PREA and PREB are made to be“L” level so that the node N1 which is the gate electrode of the MOScapacitor Qd1 and the node N2 which is the gate electrode of the MOScapacitor Qd2 are brought to the electrically floating state. Then, theselected control gate CG2A in the block selected by the controlgate/selection gate driver 303B is made to be 0V, and the non-selectedcontrol gates CG1A, CG3A and CG4A and the selection gates SG1A and SG2Aare made to be voltage Vcc. If the threshold voltage of the selectedmemory cell transistor is 0V or lower, the voltage of the bit line islower than 1.5V. If the threshold voltage of the selected memory celltransistor is 0V or higher, the voltage of the bit line is maintained at1.8V. Then, the transfer gate drive signals BLCA and BLCB are made to be“H” level so that the bit lines BLa and BLb are temporarily connected tothe nodes N1 and N2. Then, transfer gate drive signals BLCA and BLCB aremade to be “L” level so that the bit lines BLa and BLb and the nodes N1and N2 are again separated from each other.

[0949] Then, the sense amplifier activating signal SAN1 is made to be“L” level and the sense amplifier activating signal SAP1 is made to be“H” level so that the first flip-flop circuit 314A-1 is deactivated.Then, the equalizing signal ECH1 is made to be “H” level so as toequalize the node N3 and the node N4. Then, the transfer gate drivesignals RV1A and RV1B are made to be “H” level. Then, the senseamplifier activating signal SAN1 is made to be “H” level, and the senseamplifier activating signal SAP1 is made to be “L” level so that thefirst flip-flop circuit 314A-1 is activated. As a result, the voltage ofthe node N1 is sensed and latched by the first flip-flop circuit 314A-1.Thus, whether data read from the memory cell transistor is “0” or “1 or2” is sensed and latched by the first flip-flop circuit 314A-1.

[0950] Then, the selected control gate CG2A is made to be 1.5V. The bitline precharge signals PREA and PREB are made to be “H” level so thatthe node N1 which is the gate electrode of the MOS capacitor Qd1 iselectrically charged to 1.8V and the node N2 which is the gate electrodeof the MOS capacitor Qd2 is electrically charged to 1.5V. Then, the bitline precharge signals PREA and PREB are made to be “L” level so thatthe nodes N1 and N2 are brought to the electrically floating state. Ifthe threshold voltage of the selected memory cell transistor is 1.5V orlower, the voltage of the bit line is lower than 1.5V. If the thresholdvoltage of the selected memory cell transistor is 1.5V or higher, thevoltage of the bit line is maintained at 1.8V.

[0951] Then, the transfer gate drive signals BLCA and BLCB are made tobe “H” level so that the bit lines BLa and BLb are temporarily connectedto the nodes N1 and N2. Then, the transfer gate drive signals BLCA andBLCB are made to be “L” level so that the bit line BLa and BLb and thenodes N1 and N2 are again separated from each other. Then, the senseamplifier activating signal SAN2 is made to be “L” level and the senseamplifier activating signal SAP2 is made to be “H” level so that thesecond flip-flop circuit 314A-2 is deactivated. Then, the equalizingsignal ECH2 is made to be “H” level to equalize the node N5 and the nodeN6. Then, the transfer gate drive signals RV2A and RV2B respectively aremade to be “H” level. Then, the sense amplifier activating signal SAN2is made to be “H” level and the sense amplifier activating signal SAP2is made to be “L” level so that the second flip-flop circuit 314A-2 isactivated. As a result, the voltage of the node N1 is sensed and latchedby the second flip-flop circuit 314A-2. Thus, whether data read from thememory cell transistor is “2” or “0 or 1” is sensed and latched by thesecond flip-flop circuit 314A-2. The data controller 310A formed of thetwo first flip-flop circuits 314A-1 and 314A-2 is able to distinguishand store data read from the memory cell transistor whether it is “0” or“1” or “2”. Thus, the data circuit 306A is able to store read data.

[0952] The bit line voltage BLa indicated as (*4) is voltage when datain the memory cell transistor is “1” and “2”, voltage indicated as (*5)is voltage when data in the memory cell transistor is “0”, voltageindicated as (*6) is voltage when data in the memory cell transistor is“2” and voltage indicated as (*7) is voltage when data in the memorycell transistor is “0” and “1”.

[0953] During the foregoing read operation, the verify signals VRFYBAand VRFYBB are “H” level. The voltages VSa and VSb of the source line ofthe memory cell transistor are 0V.

[0954] Then, the column activating signal CENB to be supplied to thecolumn address decoder is made to be “H” level so that data read fromone of the data circuits 306A selected in response to the address signalis output to the data input/output lines I/OA, I/OB, I/OC and I/OD. Atthis time, the data circuits 306A in the even and odd number columnsarranged adjacently output two ternary data, for example, as shown inFIG. 104, so as to be supplied to the data input/output buffer 305. Thedata input/output buffer 305 is supplied with ternary data×2. The datainput/output buffer 305 converts the two ternary data into 3-bit andeight-level external read data to output the same to the outside of theEEPROM.

[0955]FIGS. 107 and 108 are operation waveforms showing the verify readoperation which is performed by the EEPROM according to the twelfthembodiment of the present invention. FIG. 108 shows timings followingtimings shown in FIG. 107.

[0956] Initially, the voltage VA is made to be 1.8V and the voltage VBis made to be 1.5V. As a result, the bit line BLa is electricallycharged to 1.8V and the bit line BLb is electrically charged to 1.5V.Then, the transfer gate drive signals BLCA and BLCB are made to be “L”level so that the bit line BLa and the MOS capacitor Qd1 are separatedfrom each other and the bit line BLb and the MOS capacitor Qd2 areseparated from each other. Thus, the bit lines BLa and BLb are broughtto the electrically floating state. Then, the bit line precharge signalsPREA and PREB are made to be “L” level so that the node N1 which is thegate electrode of the MOS capacitor Qd1 and the node N2 which is thegate electrode of the MOS capacitor Qd2 respectively are brought to theelectrically floating state.

[0957] Then, the selected control gate CG2A in the block selected by thecontrol gate/selection gate driver is made to be 0.5V and thenon-selected control gates CG1A, CG3A and CG4A and the selection gatesSG1A and SG2A respectively are made to be Vcc. If the threshold voltageof the selected memory cell transistor is 0.8V or lower, the voltage ofthe bit line is lower than 1.5V. If the threshold voltage of theselected memory cell transistor is 0.5V or higher, the voltage of thebit line is maintained at 1.8V. Then, the transfer gate drive signalsBLCA and BLCB are made to be “H” level so that the bit lines BLa and BLbare temporary connected to the nodes N1 and N2. Then, the transfer gatedrive signals BLCA and BLCB are made to be “L” level so that the bitlines BLa and BLb and the nodes N1 and N2 are again separated from eachother.

[0958] Then, the transfer gate drive signal RVA2A is made to be 1.5Vwhich is lower than the voltage Vcc. When the threshold voltage of then-channel MOS transistor Qn33 having a gate for receiving the drivesignal RVA2A is made to be 1V, the n-channel MOS transistor Qn33 in thedata circuit 306A storing write data “2” is turned on and the node N1 ismade to be 0V. On the other hand, the n-channel MOS transistor Qn33 ofthe data circuit 306A storing write data “0” or “1” is turned off sothat the node N1 is maintained at voltage of 0.5V or higher. Then, theverify signal VRFYBA is made to be “L” level. Thus, write data “0”corresponds to turning on of the p-channel MOS transistor Qp15 in thedata circuit 306A so that the node N1 is made to be voltage Vcc.

[0959] Then, the sense amplifier activating signal SAN1 is made to be“L” level and the sense amplifier activating signal SAP1 is made to be“H” level so that the first flip-flop circuit 314A-1 is deactivated.Then, the equalizing signal ECH1 is made to be “H” level so as toequalize the node N3 and the node N4. Then, the transfer gate drivesignals RV1A and RV1B are made to be “H” level. Then, the senseamplifier activating signal SAN1 is made to be “H” level and the senseamplifier activating signal SAP1 is made to be “L” level so that thefirst flip-flop circuit 314A-1 is activated. Thus, the voltage ofthe-node N1 is sensed and latched by the first flip-flop circuit 314A-1.As a result, whether or not data in the memory cell transistorcorresponding to only the data circuit 306A storing write data “1” hasbeen sufficiently brought to the state of data “1” can be detected. Ifthe memory cell transistor has been brought to the state of data “1”,the first flip-flop circuit 314A-1 senses and latches the voltage of thenode N1. Thus, write data is changed to “0”. If the memory celltransistor has been brought to the state of data “1”, the firstflip-flop circuit 314A-11 senses and latches the voltage of the node N1to maintain the stored write data “1”. In the data circuit 306A storingwrite data “0” or write data “2”, data is not changed.

[0960] Referring to FIG. 107, waveform indicated as (1) is a waveformrealized in a case of the memory cell transistor storing data “0”, thatindicated as (2) is a waveform realized in a case of the memory celltransistor storing data “1” or data “2”, that indicated as (3) is awaveform realized in a case of the memory cell transistor which isarranged to store data “1” and which has not reached the state of data“1”, that indicated as (4) is a waveform realized in a case of thememory cell transistor which is arranged to store data “1” and which hasreached the state of data “1”, that indicated as (5) is a waveformrealized in a case of the memory cell transistor which is arranged tostore data “2” and which has reached the state of data “1” and thatindicated as (6) is a waveform realized in a case of the memory celltransistor which is arranged to store data “2” and which has not reachedthe state of data “1”. The voltage of the bit line BLa indicated as (*8)is voltage realized when the memory cell transistor has reached thestate of data “1”, that indicated as (*9) is voltage realized when thememory cell transistor has not reached the state of data “1”, thatindicated as (*10) is voltage realized when the memory-cell transistorhas reached the state of data “2”, and that indicated as (*11) isvoltage realized when the memory cell transistor has not reached thestate of data “2”.

[0961] Then, the selected control gate CG2A is made to be 2V. If thethreshold voltage of the data memory cell transistor is 2v or lower, thevoltage of the bit line is lower than 1.5V. If the threshold voltage ofthe selected memory cell transistor is 2V or higher, the voltage of thebit line is maintained at 1.8V. Then, the transfer gate drive signalsBLCA and BLCB are made to be “H” so that the bit lines BLa and BLbrespectively and temporarily are connected to the nodes N1 and N2. Then,the transfer gate drive signals BLCA and BLCB respectively are made tobe “L” level so that the bit lines BLa and BLb and the nodes N1 and N2are again separated from each other.

[0962] Then, the verify signal VRFYBA is made to be “L” level so thatthe node N1 is made to be the voltage Vcc in only the data circuit 306Astoring write data “0” because the p-channel MOS transistor Qp15 hasbeen turned on. Then, the sense amplifier activating signal SAN1 is madeto be “L” level and the sense amplifier activating signal SAP1 is madeto be “H” level so that the first flip-flop circuit 314A-1 isdeactivated.

[0963] Then, the equalizing signal ECH1 is made to be “H” level so as toequalize the node N3 and the node N4. Then, the transfer gate drivesignals RV1A and RV1B are made to be “H” level. Then, the senseamplifier activating signal SAN1 is made to be “H” level and the senseamplifier activating signal SAP1 is made to be “L” level so that thefirst flip-flop circuit 314A-1 is activated. Thus, the voltage of thenode N1 is sensed and latched by the first flip-flop circuit 314A-1.

[0964] Referring to FIG. 107, waveform indicated as (7) is a waveformrealized in a case of the memory cell transistor storing data “0” ordata “1”, that indicated as (8) is a waveform realized in a case of thememory cell transistor storing data “2”, that indicated as (9) is awaveform realized in a case of the memory cell transistor which isarranged to store data “1” and which has not reached the state of data“1”, that indicated as (10) is a waveform realized in a case of thememory cell transistor which is arranged to store data “1” and which hasreached the state of data “1”, that indicated as (11) is a waveformrealized in a case of the memory cell transistor which is arranged tostore data “2” and which has reached the state of data “2”, and thatindicated as (12) is a waveform realized in a case of the memory celltransistor which is arranged to store data “2” and which has notrealized the state of data “2”.

[0965] Then, write data is changed, as shown in FIG. 108.

[0966] Initially, the bit line precharge signal PREB and the transfergate drive signal RV2A respectively are made to be “H” level. As aresult, the potential of the node N2 is made to be 1.5V and thepotential of the node N1 is made to be the level determined inaccordance with data in the second flip-flop circuit 314A-2. Then, theverify signal VRFYBA is made to be “L” level. As a result, the potentialof the node N1 is made to be the level determined in accordance withdata in the first flip-flop circuit 314A-1. Then, the sense amplifieractivating signal SAN2 is made to be “L” and the sense amplifieractivating signal SAP2 is made to be “H” level so that the secondflip-flop circuit 314A-2 is deactivated. Then, the equalizing signalECH2 is made to be “H” level to equalize the node N5 and the node N6.

[0967] Then, the transfer gate drive signals RV2A and RV2B respectivelyare made to be “H” level. Then, the sense amplifier activating signalSAN2 is made to be “H” level and the sense amplifier activating signalSAP2 is made to be “L” level to activate the second flip-flop circuit314A-2. As a result, the voltage of the node N1 is sensed and latched bythe second flip-flop circuit 314A-2.

[0968] Therefore, whether or not data in the memory cell transistorcorresponding to only the data circuit 306A storing write data “2” hassufficiently be brought to the state of data “2” can be detected. If thememory cell transistor has brought to the state of data “2”, the firstflip-flop circuit 314A-1 and the second flip-flop circuit 314A-2respectively sense and latch the voltage of the node N1. As a result,write data is changed to “0”. If the memory cell transistor has notbrought to the state of data “2”, the first flip-flop circuit 314A-1 andthe second flip-flop circuit 314A-2 respectively sense and latch thevoltage of the node N1 to maintain stored write data “2”. In the datacircuit 306A storing write data “0” or write data “1”, data is notchanged.

[0969] During the verify read operation, the verify signal VRFYBB is “H”level and the voltage VS of the source line of the memory celltransistor is 0V.

[0970] If all of the selected memory cell transistors have reachedrequired threshold voltages, all of write data items in the datacircuits 306A-0 to 306A-m are made to be “0”. By detecting this, whetheror not all of the selected memory cell transistors have reached requiredthreshold voltages can be detected.

[0971]FIG. 109 is a table showing a state in which write data in thedata circuit 306A is changed.

[0972] Although the EEPROM according to the twelfth embodiment has thestructure such that the potential of the bit line corresponding to thedata circuit 306A storing write data “1” is made to be the bit linewrite control voltage which is 1.5V , the voltage may be 0V. Similarlyto the structure shown in FIG. 92, write operation is performed after afact has been confirmed that data has sufficiently reached the requiredstate.

[0973] (Thirteenth Embodiment)

[0974]FIG. 110 is a diagram showing the structures of a memory cellarray 301 and a column-system circuit 303 of an EEPROM according to athirteenth embodiment of the present invention.

[0975] The tenth and eleventh embodiments have the structure such thatone data circuit 306 corresponds to one bit line BL. A structure may beemployed in which one data circuit 306 corresponds to a plurality of bitlines BL.

[0976] As shown in FIG. 110, the EEPROM according to the thirteenthembodiment has a structure such that one of the data circuits 306-0 to306-m is provided for four bit lines BLi-1 to BLi-4 (i is 0 to 3). Whenthe bit line BLi-1 is selected from four bit lines BLi-1 to Bli-4, thesignal BLC1 of the drive signals BLC1 to BLC4 for driving the transfergate circuit 307-1 in the data circuit portion is made to be “H” level.Moreover, the other signals BLC2 to BLC4 respectively are made to be “L”level.

[0977] Simultaneously, the signal BLC1D of the drive signals BLC1D toBLC4D for driving the transfer gate circuit 307-2 in the portionincluding the non-selected bit line controller 320 is made to be “L”level. Moreover, the other signals BLC2D to BLC4D respectively are madeto be “H” level. As a result, only the selected bit line BLi-1 isconnected to the data circuits 306-0 to 306-m. The non-selected bitlines BLi-2 to BLi-4 respectively are connected to the non-selected bitline controllers 320-0 to 320-m. The non-selected bit line controllers320-0 to 320-m control the potentials of the non-selected bit linesBLi-2 to BLi-4.

[0978] (Fourteenth Embodiment)

[0979]FIG. 111 is a diagram showing the structures of a memory cellarrays 301A and 301B and a column-system circuit of an EEPROM accordingto a fourteenth embodiment of the present invention.

[0980] Also the twelfth embodiment has the structure such that one datacircuit 306 corresponds to one bit line BLa (or BLb), similarly to thetenth and eleventh embodiments. A modification may be employed in whichone data circuit 306 corresponds to a plurality of bit lines BLa (orBLb). A modification of the twelfth embodiment will now be described asthe fourteenth embodiment.

[0981] Also the EEPROM according to the fourteenth embodiment structuredas shown in FIG. 111 has a structure such that one bit line selectedfrom four bit lines BLi-1 to BLi-4 (i is 0 to 3) and the data circuits306-0 to 306-m are connected and three non-selected bit lines and thenon-selected bit line controllers 320-0 to 320-m are connected.

[0982] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the present invention in itsbroader aspects is not limited to the specific details, representativedevices, and illustrated examples shown and described herein.Accordingly, various modifications may be made without departing fromthe spirit or scope of the general inventive concept as defined by theappended claims and their equivalents.

[0983] Although the foregoing embodiment has been made about thestructure in which the NAND cells are integrated in the memory cellarray, the present invention is not limited to this. The following-cellmay be employed in the present invention.

[0984]FIG. 112 is a diagram showing a memory cell array having NOR cellsintegrated therein. The NOR cells shown in FIG. 112 are connected to thebit line BL through the selection gate transistor.

[0985]FIG. 113 is a diagram showing a memory cell array having other NORcells integrated therein. The NOR cells shown in FIG. 113 are directlyconnected to the bit line BL.

[0986]FIG. 114 is a diagram showing a memory cell array having groundarray cells integrated therein. As shown in FIG. 114, the ground arraycell has a structure such that the bit line BL and the source line VSare arranged in parallel to each other. The ground array cell is one ofthe NOR type memory.

[0987]FIG. 115 is a diagram showing a memory cell array having anothertype ground array cells-integrated therein. The ground array cell shownin FIG. 115 has an erasing gate EG for use to erase data. Moreover, thecell has a so-called split channel structure in which a portion of thecontrol gate CG overlaps the channel of the memory cell transistor.

[0988]FIG. 116 is a diagram showing a memory cell array having analternate ground array cells integrated therein. As shown in FIG. 116,the alternate ground array cell has a structure similar to the groundarray cell in the viewpoint that the bit line BL and the source line VSare arranged in parallel to each other. However, it is different fromthe ground array cell in that the bit line BL and the source line VS arealternately switched.

[0989]FIG. 117 is a diagram showing a memory cell array having anothertype alternate ground array cells integrated therein. The alternateground array cell shown in FIG. 117 has a structure similar to that ofthe ground array cell shown in FIG. 117.

[0990]FIG. 118 is a diagram showing a memory cell array having DINOR(Divided NOR) cells integrated therein. As shown in FIG. 118, the DINORcell has a structure such that, for example, four memory celltransistors are, in parallel, connected between the bit line BL and thesource line VS through a bit line side selection transistor.

[0991]FIG. 119 is a diagram showing a memory cell array having AND cellsintegrated therein. As shown in FIG. 119, the AND cell has a structuresuch that, for example, four memory cell transistors are, in parallel,connected between the bit line BL and the source line VS through abit-line side selection transistor and a source-line side selectiontransistor.

[0992] Although the four-level storing EEPROM has been described in theforegoing embodiments, the present invention may be applied to an EEPROMcapable of storing n-level (n≧3).

[0993] Although the foregoing embodiments have the structure such thatdata in the memory cell is read as the voltage level which has appearedon the bit line BL, data may be read as a level of an electric currentwhich flows the bit line BL.

[0994] As described above, according to the present invention, there isprovided a nonvolatile semiconductor memory device capable of decreasingthe size of the column-system circuit by decreasing the number of thesense amplifiers and data latches and therefore realizing a highlyintegrated structure.

[0995] Moreover, a nonvolatile semiconductor memory device can beprovided which is capable of omitting a circuit for converting thenumber of bits and simultaneously realizing high integration andhigh-speed-input/output operation.

1. A nonvolatile semiconductor memory device comprising: a memory cellarray in which memory cells for storing multilevel data are arranged ina matrix manner; a bit line controller having latching means forlatching data to be written in said memory cell when data is written insaid memory cell and sensing/latching means for sensing and latchingdata read from said memory cell when data is read from said memory cell;and a bit line for electrically connecting said bit line controller andsaid memory cell to each other, supplying data from said latching meansto said memory cell when data is written in said memory cell andsupplying read data from said memory cell to said sensing/latching meanswhen data is read from said memory cell, wherein when said number ofmultilevel data is n (n is a natural number not smaller than 4), saidnumber of said latching means and the number of said sensing/latchingmeans are m (m satisfies 2^(m−1)<n≦2^(m) (m is a natural number notsmaller than 2).
 2. The nonvolatile semiconductor memory deviceaccording to claim 1, in which, when the number of multilevel data is nsatisfying n=2^(m), m is the same as the number of bits of datainput/output lines which are electrically connected to said bit linecontroller, and one bit data is assigned to each of said m latchingmeans and said m sensing/latching means.
 3. The nonvolatilesemiconductor memory device according to claim 2, in which, when data isread from said memory cell, said m sensing/latching means aresequentially operated from first sensing/latching means assigned to afirst bit which is the most significant bit toward said m-thsensing/latching means assigned to said m-th bit which is the leastsignificant bit.
 4. The nonvolatile semiconductor memory deviceaccording to claim 3, in which said first sensing/latching meansassigned to the first bit which is the most significant bit comparesread data supplied from said memory cell through said bit line with afirst reference voltage to output a result of a comparison representingwhether or not read data is higher than the first reference voltage, andswitches the level of a second reference voltage to be provided for asecond sensing/latching means assigned to a second bit which is a nextbit in accordance with the output result of the comparison.
 5. Thenonvolatile semiconductor memory device according to claim 4, in whichthe level of said m-th reference voltage to be provided for asensing/latching means assigned to said m-th bit which is the leastsignificant bit is switched 2^(m−1) times in accordance with a result ofa comparison between said (m−1)-th reference voltage provided for saidsensing/latching means assigned to said (m−1)-th bit which is an upperbit and data read from said memory cell.
 6. The nonvolatilesemiconductor memory device according to claim 2, in which the number ofbits of said data input/output line is the same as the number of bits ofwrite data to be supplied to said apparatus from outside of saidapparatus and the number of bits of read data to be output from theinside portion of said apparatus to the outside of said apparatus. 7.The nonvolatile semiconductor memory device according to claim 6, inwhich the write data is supplied to said latching means from outside ofsaid apparatus such that the number of bits of write data is notconverted, and read data is output from said sensing/latching means tothe outside of said apparatus such that the number of bits of read datais not converted.
 8. The nonvolatile semiconductor memory deviceaccording to claim 7, in which 2^(m) =n-level data, which appears on onebit line, is converted into m-bit and n-level data by said latchingmeans and said sensing/latching means.
 9. The nonvolatile semiconductormemory device according to claim 1, in which each of the write data tobe supplied from said latching means to said memory cell through saidbit line and read data to be supplied from said memory cell to saidsensing/latching means through said bit line is n multilevel data, andsaid bit line distinguishes each of n multilevel data in accordance withthe level of voltage to supply data from said latching means to saidmemory cell and supply data from said memory cell to saidsensing/latching means.
 10. The nonvolatile semiconductor memory deviceaccording to claim 2, in which each of the write data to be suppliedfrom said latching means to said memory cell through said bit line andread data to be supplied from said memory cell to said sensing/latchingmeans through said bit line is n multilevel data, and said bit linedistinguishes each of n multilevel data in accordance with the level ofvoltage to supply data from said latching means to said memory cell andsupply data from said memory cell to said sensing/latching means. 11.The nonvolatile semiconductor memory device according to claim 1, inwhich said memory cell for storing multilevel data includes a transistorhaving a variable threshold voltage, and said transistor having thevariable threshold voltage distinguishes each of n multilevel data inaccordance with the level of the threshold voltage and then store nmultilevel data.
 12. A nonvolatile semiconductor memory devicecomprising: a memory cell array in which memory cells for storingmultilevel data are arranged in a matrix manner; a bit line controllerhaving latching means for latching data to be written in said memorycell when data is written in said memory cell, sensing/latching meansfor sensing and latching data read from said memory cell when data isread from said memory cell and verify means for performing a verifyoperation to make a reference to data latched by said latching means andarranged to be written in said memory cell; and a bit line forelectrically connecting said bit line controller and said memory cell toeach other, supplying data from said latching means into said memorycell when data is written in said memory cell and supplying read datafrom said memory cell to said sensing/latching means when data is readfrom said memory cell, wherein when the number of multilevel data is n(n is a natural number not smaller than 4), the number of said latchingmeans, the number of said sensing/latching means and the number of saidverify means are m (m satisfies 2^(m−1)<n≦2^(m) (m is a natural numbernot smaller than 2).
 13. The nonvolatile semiconductor memory deviceaccording to claim 12, in which, when the number of multilevel data is nsatisfying n=2^(m), m is the same as the number of bits of datainput/output lines which are electrically connected to said bit linecontroller, and one bit data is assigned to each of said m latchingmeans and said m sensing/latching means.
 14. The nonvolatilesemiconductor memory device according to claim 13, in which, when datais read from said memory cell, said m sensing/latching means aresequentially operated from first sensing/latching means assigned to afirst bit which is the most significant bit toward said m-thsensing/latching means assigned to said m-th bit which is the leastsignificant bit, and when data is read from said memory cell forverification, said m sensing/latching means are sequentially operatedfrom m-th sensing/latching means assigned to m-th bit which is saidleast significant bit toward said first sensing/latching means assignedto said first bit which is the most significant bit.
 15. The nonvolatilesemiconductor memory device according to claim 14, in which, when datais read from said memory cell, said first sensing/latching meansassigned to said first bit which is the most significant bit comparesread data supplied from said memory cell through said bit line with afirst reference voltage to output a result of a comparison representingwhether or not read data is higher than the first reference voltage, andswitches the level of a second reference voltage to be provided for asecond sensing/latching means assigned to a second bit which is a nextbit in accordance with the output result of the comparison, and whendata is read from said memory cell for verification, the level of thesecond reference voltage to be provided for said second sensing/latchingmeans assigned to the second bit which is the next bit is switched inaccordance with read data latched by said first latching means assignedto the first bit which is the most significant bit.
 16. The nonvolatilesemiconductor memory device according to claim 15, in which, when datais read from said memory cell, the level of the m-th reference voltageto be provided for a sensing/latching means assigned to the m-th bitwhich is the least significant bit is switched 2^(m−1) times inaccordance with a result of a comparison between the (m−1)-th referencevoltage provided for said sensing/latching means assigned to the(m−1)-th bit which is an upper bit and data read from said memory cell.17. The nonvolatile semiconductor memory device according to claim 16,in which, when data is read from said memory cell, said sensing/latchingmeans converts 2^(m)=n-level data read to one bit line into n m-bit readdata, when data is written in said memory cell, said latching meanssupplies m-bit n-level write data to data writing circuit for convertingdata into 2^(m)=n-level write data for one bit line, and m-bit andn-level read data and m-bit and n-level write data are supplied asdifferent data.
 18. The nonvolatile semiconductor memory deviceaccording to claim 17, in which, when data is read from said memory cellfor verification, said latching means compares m-bit n-level write datawith 2^(m)=n-level data read to one bit line, activates said verifymeans when the write data and the read data coincide with each other anddeactivates said verify means when the write data and the read data donot coincide with each other.
 19. The nonvolatile semiconductor memorydevice according to claim 13, the number of bits of said datainput/output lines is the same as each of the number of bits of writedata to be supplied from outside of said apparatus into said apparatusand the number of bits of read data to be output from the inside portionof said apparatus to the outside of said apparatus.
 20. The nonvolatilesemiconductor memory device according to claim 19, write data issupplied from the outside of said apparatus to said latching means suchthat the number of bits of write data is not converted, and read data isoutput from said sensing/latching means to the outside of said apparatussuch that the number of bits of read data is not converted.
 21. Thenonvolatile semiconductor memory device according to claim 12, each ofwrite data to be supplied from said latching means to said memory cellthrough said bit line and read data to be supplied from said memory cellto said sensing/latching means through said bit line is n multileveldata, and said bit line distinguishes each of n multilevel data inaccordance with the level of voltage to supply data from said latchingmeans to said memory cell and supply data from said memory cell to saidsensing/latching means.
 22. The nonvolatile semiconductor memory deviceaccording to claim 13, each of write data to be supplied from saidlatching means to said memory cell through said bit line and read datato be supplied from said memory cell to said sensing/latching meansthrough said bit line is n multilevel data, and said bit linedistinguishes each of n multilevel data in accordance with the level ofvoltage to supply data from said latching means to said memory cell andsupply data from said memory cell to said sensing/latching means. 23.The nonvolatile semiconductor memory device according to claim 12, saidmemory cell for storing multilevel data includes a transistor having avariable threshold voltage, and said transistor having the variablethreshold voltage distinguishes each of n multilevel data in accordancewith the level of the threshold voltage and then store n multileveldata.
 24. A nonvolatile semiconductor memory device comprising: a memorycell array in which memory cells for storing multilevel data arearranged in a matrix manner; a bit line controller having latchingfunction for latching data to be written in said memory cell when datais written in said memory cell and sensing/latching function for sensingand latching data read from said memory cell when data is read from saidmemory cell and in which when the number of multilevel data is n (n is anatural number not smaller than 4), the number of said latching functionand the number of said sensing/latching function are m (m satisfies2^(m−1)<n≦2^(m) (m is a natural number not smaller than 2); a bit linefor electrically connecting said bit line controller and said memorycell to each other, supplying data from said latching function into saidmemory cell when data is written in said memory cell and supplying readdata from said memory cell to said sensing/latching function when datais read from said memory cell; a writing circuit for selecting writecontrol voltage corresponding to multilevel data in accordance withwrite data latched by said latching function when data is written insaid memory cell and applying selected write control voltage to said bitline; and a verify circuit for verifying data written in said memorycell, wherein said verify circuit and said writing circuit is controlledin accordance with n write data latched by said latching function.
 25. Anonvolatile semiconductor memory device comprising: a memory cell arrayin which memory cells for storing multilevel data are arranged in amatrix manner; a bit line controller having data latch/sense amplifierfor latching data to be written in said memory cell when data is writtenin said memory cell and sensing and latching data read from said memorycell when data is read from said memory cell such that when the numberof multilevel data is 2^(m) (m is a natural number not smaller than2)=n-level, the number of said data latch/sense amplifier is m; a bitline for connecting said data latch/sense amplifier and said memory cellto each other, supplying data from said data latch/sense amplifier intosaid memory cell when data is written in said memory cell and supplyingread data from said memory cell to said data latch/sense amplifier whendata is read from said memory cell; a writing circuit for selectingwrite control voltage corresponding to multilevel data in accordancewith write data latched by said data latch/sense amplifier when data iswritten in said memory cell and applying selected write control voltageto the bit line; and a verify circuit for verifying whether or notwritten data has been brought to a required date storing state afterdata has been written in said memory cell.
 26. A nonvolatilesemiconductor memory device comprising: means for charging the bit linewith one of bit line write potentials corresponding to multilevel datawhen multilevel data is written in said memory cell and brining the bitline to an electrically floating state; and means for causing thepotential of said bit line to have a bit line write control potentialdetermined in accordance with multilevel data by increasing, decreasingor maintaining the quantity of charge of said bit line.
 27. Anonvolatile semiconductor memory device comprising: memory cell array inwhich memory cells for storing binary or higher level data are arrangedin a matrix manner; a bit line used for writing data in said memory celland reading data from said memory cell; and a bit line controller formaking the bit line to a predetermined potential and then bringing thebit line to an electrically floating state, wherein said bit line is setto a predetermined potential and when data is written in said memorycell, the predetermined potential of said bit line is used as one of bitline write control voltages.
 28. A nonvolatile semiconductor memorydevice comprising: a memory cell array in which memory cells for storingbinary or higher level data are arranged in a matrix manner; a bit linefor transferring data to be written in said memory cell and data readfrom said memory cell; a first circuit connected to said bit line tomake the potential of said bit line to a predetermined level before datais written in said memory cell and bring said bit line to anelectrically floating state; and a second circuit connected to said bitline for maintaining the potential of said bit line at the predeterminedlevel when one of binary or higher level data is written in a selectedmemory cell and shifting the potential of the bit line to a leveldifferent from the predetermined level when another binary or higherlevel data is written in a selected memory cell.
 29. The nonvolatilesemiconductor memory device according to claim 28, in which said secondcircuit includes a flip-flop circuit, and said flip-flop circuit storesdata to be written when data is written in said memory cell.
 30. Thenonvolatile semiconductor memory device according to claim 29, in whichsaid flip-flop circuit maintains the potential of said bit line at thepredetermined level or shifts the potential to a level different fromthe predetermined level in accordance with stored data to be writtenwhen data is written in said memory cell.
 31. The nonvolatilesemiconductor memory device according to claim 29, in which saidflip-flop circuit amplifies and stores read data when data is read fromsaid memory cell.
 32. The nonvolatile semiconductor memory deviceaccording to claim 30, in which said flip-flop circuit amplifies andstores read data when data is read from said memory cell.
 33. Thenonvolatile semiconductor memory device according to claim 29, in whichthe number of data to be stored by said memory cell is n (n≧2), thenumber of said flip-flop circuits for storing data to be written in saidmemory cell and amplifies and stores data read from said memory cell is(n−1).
 34. The nonvolatile semiconductor memory device according toclaim 30, in which the number of data to be stored by the memory cell isn (n−2), the number of said flip-flop circuits for storing data to bewritten in said memory cell and amplifies and stores data read from saidmemory cell is (n−1).
 35. The nonvolatile semiconductor memory deviceaccording to claim 31, in which the number of data to be stored by saidmemory cell is n (n≧2), the number of said flip-flop circuits forstoring data to be written in said memory cell and amplifies and storesdata read from said memory cell is (n−1).
 36. The nonvolatilesemiconductor memory device according to claim 32, in which the numberof data to be stored by said memory cell is n (n≧2), the number of saidflip-flop circuits for storing data to be written in said memory celland amplifies and stores data read from said memory cell is (n−1) 37.The nonvolatile semiconductor memory device according to claim 33, inwhich write data stored by (n−1) flip-flop circuits is changed toanother data after a verify operation has been completed.
 38. Thenonvolatile semiconductor memory device according to claim 34, in whichwrite data stored by (n−1) flip-flop circuits is changed to another dataafter a verify operation has been completed.
 39. The nonvolatilesemiconductor memory device according to claim 35, in which write datastored by (n−1) flip-flop circuits is changed to another data after averify operation has been completed.
 40. The nonvolatile semiconductormemory device according to claim 36, in which write data stored by (n−1)flip-flop circuits is changed to another data after a verify operationhas been completed.
 41. The nonvolatile semiconductor memory deviceaccording to claim 37, further comprising a write completion detectingcircuit for detecting change of write data stored by (n−1) flip-flopcircuits into another data to complete a writing operation when saidwrite completion detecting circuit has detected the change.
 42. Thenonvolatile semiconductor memory device according to claim 38, furthercomprising a write completion detecting circuit for detecting change ofwrite data stored by (n−1) flip-flop circuits into another data tocomplete a writing operation when said write completion detectingcircuit has detected the change.
 43. The nonvolatile semiconductormemory device according to claim 39, further comprising a writecompletion detecting circuit for detecting change of write data storedby (n−1) flip-flop circuits into another data to complete a writingoperation when said write completion detecting circuit has detected thechange.
 44. The nonvolatile semiconductor memory device according toclaim 40, further comprising a write completion detecting circuit fordetecting change of write data stored by (n−1) flip-flop circuits intoanother data to complete a writing operation when said write completiondetecting circuit has detected the change.
 45. A nonvolatilesemiconductor memory device comprising: a memory cell array in whichmemory cell for storing binary or higher level data are arranged in amatrix manner; a bit line connected to a source and a drain of saidmemory cell; and a bit line controller connected between said bit lineand a data input/output line, wherein said bit line controller has acharging circuit for charging the bit line before a writing operation, awrite data storing portion for storing write data supplied to said datainput/output line, and a data controller for maintaining the potentialof said bit line at the charged level or shifting the potential from thecharged level in accordance with write data stored by the write datastoring portion.
 46. The nonvolatile semiconductor memory deviceaccording to claim 45, in which said data controller includes aflip-flop circuit, and said flip-flop circuit stores write data suppliedto said data input/output line when data is written in said memory cell.47. The nonvolatile semiconductor memory device according to claim 46,in which said flip-flop circuit amplifies data read to the bit line tosupply read data to said data input/output line.
 48. The nonvolatilesemiconductor memory device according to claim 46, in which, when thenumber of data to be stored by said memory cell is n (n≧2), the numberof said flip-flop circuits for storing data to be written in said memorycell and amplifies and stores data read from said memory cell is (n−1).49. The nonvolatile semiconductor memory device according to claim 47,in which, when the number of data to be stored by said memory cell is n(n≧2), the number of said flip-flop circuits for storing data to bewritten in said memory cell and amplifies and stores data read from saidmemory cell is (n−1).
 50. The nonvolatile semiconductor memory deviceaccording to claim 48, in which said write data stored by (n−1)flip-flop circuits is changed to another data after a verificationoperation has been completed.
 51. The nonvolatile semiconductor memorydevice according to claim 49, in which the write data stored by (n−1)flip-flop circuits is changed to another data after a verificationoperation has been completed.
 52. The nonvolatile semiconductor memorydevice according to claim 50, further comprising a write completiondetecting circuit for detecting change of write data stored by (n−1)flip-flop circuits into another data to complete a writing operationwhen said write completion detecting circuit has detected the change.53. The nonvolatile semiconductor memory device according to claim 51,further comprising a write completion detecting circuit for detectingchange of write data stored by (n−1) flip-flop circuits into anotherdata to complete a writing operation when said write completiondetecting circuit has detected the change.
 54. The nonvolatilesemiconductor memory device according to claim 45, in which saidcharging circuit charges the bit line to a power supply potential. 55.The nonvolatile semiconductor memory device according to claim 54, inwhich said data controller maintains the potential of the bit line atthe power supply potential or makes the potential to be lower than thepower supply potential.
 56. The nonvolatile semiconductor memory deviceaccording to claim 45, in which said charging circuit charges the bitline to a potential between a ground voltage and the power supplyvoltage.
 57. The nonvolatile semiconductor memory device according toclaim 56, in which said data controller maintains the potential of thebit line at the intermediate potential, makes the potential to be lowerthan the intermediate potential or makes the potential to be higher thanthe intermediate potential in accordance with write data stored by saidwrite data storing portion included in said data controller.